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/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v5_0_1.c74 if (!adev->jpeg.num_jpeg_inst || adev->jpeg.num_jpeg_inst > AMDGPU_MAX_JPEG_INSTANCES) in jpeg_v5_0_1_early_init()
77 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; in jpeg_v5_0_1_early_init()
97 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v5_0_1_sw_init()
100 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); in jpeg_v5_0_1_sw_init()
113 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v5_0_1_sw_init()
116 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v5_0_1_sw_init()
117 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v5_0_1_sw_init()
119 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); in jpeg_v5_0_1_sw_init()
134 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); in jpeg_v5_0_1_sw_init()
135 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v5_0_1_sw_init()
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H A Djpeg_v2_5.c63 adev->jpeg.num_jpeg_rings = 1; in jpeg_v2_5_early_init()
64 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS; in jpeg_v2_5_early_init()
65 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in jpeg_v2_5_early_init()
68 adev->jpeg.harvest_config |= 1 << i; in jpeg_v2_5_early_init()
70 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 | in jpeg_v2_5_early_init()
94 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_sw_init()
95 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_sw_init()
100 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); in jpeg_v2_5_sw_init()
106 VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); in jpeg_v2_5_sw_init()
112 VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); in jpeg_v2_5_sw_init()
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H A Djpeg_v4_0_5.c74 adev->jpeg.num_jpeg_inst = 1; in jpeg_v4_0_5_early_init()
77 adev->jpeg.num_jpeg_inst = 2; in jpeg_v4_0_5_early_init()
86 adev->jpeg.num_jpeg_rings = 1; in jpeg_v4_0_5_early_init()
107 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_sw_init()
108 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_sw_init()
113 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
119 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
125 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
138 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_sw_init()
139 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_sw_init()
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H A Djpeg_v4_0_3.c79 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; in jpeg_v4_0_3_early_init()
101 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
104 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); in jpeg_v4_0_3_sw_init()
117 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_sw_init()
120 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
121 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v4_0_3_sw_init()
123 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); in jpeg_v4_0_3_sw_init()
138 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); in jpeg_v4_0_3_sw_init()
139 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v4_0_3_sw_init()
144 adev->jpeg.internal.jpeg_pitch[j] = in jpeg_v4_0_3_sw_init()
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H A Djpeg_v4_0.c60 adev->jpeg.num_jpeg_inst = 1; in jpeg_v4_0_early_init()
61 adev->jpeg.num_jpeg_rings = 1; in jpeg_v4_0_early_init()
85 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v4_0_sw_init()
91 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v4_0_sw_init()
97 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v4_0_sw_init()
109 ring = adev->jpeg.inst->ring_dec; in jpeg_v4_0_sw_init()
115 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v4_0_sw_init()
120 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v4_0_sw_init()
121 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); in jpeg_v4_0_sw_init()
127 adev->jpeg.supported_reset = in jpeg_v4_0_sw_init()
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H A Djpeg_v5_0_0.c53 adev->jpeg.num_jpeg_inst = 1; in jpeg_v5_0_0_early_init()
54 adev->jpeg.num_jpeg_rings = 1; in jpeg_v5_0_0_early_init()
77 VCN_5_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v5_0_0_sw_init()
89 ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_sw_init()
95 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v5_0_0_sw_init()
100 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v5_0_0_sw_init()
101 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); in jpeg_v5_0_0_sw_init()
104 adev->jpeg.supported_reset = in jpeg_v5_0_0_sw_init()
105 amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); in jpeg_v5_0_0_sw_init()
143 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_hw_init()
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H A Djpeg_v3_0.c66 adev->jpeg.num_jpeg_inst = 1; in jpeg_v3_0_early_init()
67 adev->jpeg.num_jpeg_rings = 1; in jpeg_v3_0_early_init()
90 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v3_0_sw_init()
102 ring = adev->jpeg.inst->ring_dec; in jpeg_v3_0_sw_init()
107 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v3_0_sw_init()
112 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v3_0_sw_init()
113 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); in jpeg_v3_0_sw_init()
148 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v3_0_hw_init()
167 cancel_delayed_work_sync(&adev->jpeg.idle_work); in jpeg_v3_0_hw_fini()
169 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v3_0_hw_fini()
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H A Djpeg_v2_0.c52 adev->jpeg.num_jpeg_inst = 1; in jpeg_v2_0_early_init()
53 adev->jpeg.num_jpeg_rings = 1; in jpeg_v2_0_early_init()
76 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v2_0_sw_init()
88 ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_sw_init()
93 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, in jpeg_v2_0_sw_init()
98 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v2_0_sw_init()
99 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); in jpeg_v2_0_sw_init()
134 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_hw_init()
153 cancel_delayed_work_sync(&adev->jpeg.idle_work); in jpeg_v2_0_hw_fini()
155 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v2_0_hw_fini()
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H A Djpeg_v1_0.c447 amdgpu_fence_process(adev->jpeg.inst->ring_dec); in jpeg_v1_0_process_interrupt()
469 adev->jpeg.num_jpeg_inst = 1; in jpeg_v1_0_early_init()
470 adev->jpeg.num_jpeg_rings = 1; in jpeg_v1_0_early_init()
491 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->jpeg.inst->irq); in jpeg_v1_0_sw_init()
495 ring = adev->jpeg.inst->ring_dec; in jpeg_v1_0_sw_init()
498 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, in jpeg_v1_0_sw_init()
503 adev->jpeg.internal.jpeg_pitch[0] = adev->jpeg.inst->external.jpeg_pitch[0] = in jpeg_v1_0_sw_init()
520 amdgpu_ring_fini(adev->jpeg.inst->ring_dec); in jpeg_v1_0_sw_fini()
533 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v1_0_start()
591 adev->jpeg.inst->ring_dec->funcs = &jpeg_v1_0_decode_ring_vm_funcs; in jpeg_v1_0_set_dec_ring_funcs()
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H A Damdgpu_jpeg.h48 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
50 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
91 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset; \
92 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value; \
H A Dvcn_v1_0.c263 ring = adev->jpeg.inst->ring_dec; in vcn_v1_0_hw_init()
1264 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1265 new_state->fw_based, new_state->jpeg); in vcn_v1_0_pause_dpg_mode()
1317 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { in vcn_v1_0_pause_dpg_mode()
1320 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1321 new_state->fw_based, new_state->jpeg); in vcn_v1_0_pause_dpg_mode()
1326 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { in vcn_v1_0_pause_dpg_mode()
1348 ring = adev->jpeg.inst->ring_dec; in vcn_v1_0_pause_dpg_mode()
1374 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; in vcn_v1_0_pause_dpg_mode()
1846 if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec)) in vcn_v1_0_idle_work_handler()
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/linux/drivers/media/platform/samsung/s5p-jpeg/
H A DMakefile2 s5p-jpeg-objs := jpeg-core.o jpeg-hw-exynos3250.o jpeg-hw-exynos4.o jpeg-hw-s5p.o
3 obj-$(CONFIG_VIDEO_SAMSUNG_S5P_JPEG) += s5p-jpeg.o
/linux/drivers/media/platform/mediatek/jpeg/
H A Dmtk_jpeg_enc_hw.c187 static void mtk_jpegenc_put_buf(struct mtk_jpegenc_comp_dev *jpeg) in mtk_jpegenc_put_buf() argument
196 ctx = jpeg->hw_param.curr_ctx; in mtk_jpegenc_put_buf()
198 dev_err(jpeg->dev, "comp_jpeg ctx fail !!!\n"); in mtk_jpegenc_put_buf()
202 dst_buffer = jpeg->hw_param.dst_buffer; in mtk_jpegenc_put_buf()
204 dev_err(jpeg->dev, "comp_jpeg dst_buffer fail !!!\n"); in mtk_jpegenc_put_buf()
264 struct mtk_jpegenc_comp_dev *jpeg = priv; in mtk_jpegenc_hw_irq_handler() local
265 struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev; in mtk_jpegenc_hw_irq_handler()
267 cancel_delayed_work(&jpeg->job_timeout_work); in mtk_jpegenc_hw_irq_handler()
269 ctx = jpeg->hw_param.curr_ctx; in mtk_jpegenc_hw_irq_handler()
270 src_buf = jpeg->hw_param.src_buffer; in mtk_jpegenc_hw_irq_handler()
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H A DMakefile3 mtk-jpeg-enc-hw.o \
4 mtk-jpeg-dec-hw.o
9 mtk-jpeg-enc-hw-y := mtk_jpeg_enc_hw.o
10 mtk-jpeg-dec-hw-y := mtk_jpeg_dec_hw.o
H A DKconfig12 Mediatek jpeg codec driver provides HW capability to decode
16 module will be called mtk-jpeg
/linux/drivers/media/platform/nxp/imx-jpeg/
H A DMakefile2 mxc-jpeg-encdec-objs := mxc-jpeg-hw.o mxc-jpeg.o
3 obj-$(CONFIG_VIDEO_IMX8_JPEG) += mxc-jpeg-encdec.o
/linux/drivers/media/platform/imagination/
H A DMakefile2 e5010_jpeg_enc-objs := e5010-jpeg-enc-hw.o e5010-jpeg-enc.o
/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-g-jpegcomp.rst39 :ref:`JPEG class controls <jpeg-controls>` for image quality and JPEG
69 :ref:`V4L2_CID_JPEG_COMPRESSION_QUALITY <jpeg-quality-control>`
89 - See :ref:`jpeg-markers`. Deprecated. If
90 :ref:`V4L2_CID_JPEG_ACTIVE_MARKER <jpeg-active-marker-control>`
/linux/Documentation/driver-api/media/
H A Dv4l2-jpeg.rst6 .. kernel-doc:: include/media/v4l2-jpeg.h
9 .. kernel-doc:: drivers/media/v4l2-core/v4l2-jpeg.c
H A Dv4l2-core.rst29 v4l2-jpeg
/linux/drivers/media/platform/mediatek/
H A DMakefile2 obj-y += jpeg/
H A DKconfig5 source "drivers/media/platform/mediatek/jpeg/Kconfig"
/linux/drivers/media/platform/samsung/
H A DMakefile6 obj-y += s5p-jpeg/
/linux/drivers/media/platform/chips-media/coda/
H A DMakefile3 …a-vpu-objs := coda-common.o coda-bit.o coda-gdi.o coda-h264.o coda-mpeg2.o coda-mpeg4.o coda-jpeg.o
/linux/drivers/media/platform/nxp/
H A DMakefile4 obj-y += imx-jpeg/

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