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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_jpeg.c42 INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler); in amdgpu_jpeg_sw_init()
43 mutex_init(&adev->jpeg.jpeg_pg_lock); in amdgpu_jpeg_sw_init()
44 atomic_set(&adev->jpeg.total_submission_cnt, 0); in amdgpu_jpeg_sw_init()
48 adev->jpeg.indirect_sram = true; in amdgpu_jpeg_sw_init()
50 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in amdgpu_jpeg_sw_init()
51 if (adev->jpeg.harvest_config & (1U << i)) in amdgpu_jpeg_sw_init()
54 if (adev->jpeg.indirect_sram) { in amdgpu_jpeg_sw_init()
58 &adev->jpeg.inst[i].dpg_sram_bo, in amdgpu_jpeg_sw_init()
59 &adev->jpeg.inst[i].dpg_sram_gpu_addr, in amdgpu_jpeg_sw_init()
60 &adev->jpeg.inst[i].dpg_sram_cpu_addr); in amdgpu_jpeg_sw_init()
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H A Djpeg_v5_0_2.c116 if (!adev->jpeg.num_jpeg_inst || adev->jpeg.num_jpeg_inst > AMDGPU_MAX_JPEG_INSTANCES) in jpeg_v5_0_2_early_init()
119 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; in jpeg_v5_0_2_early_init()
139 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v5_0_2_sw_init()
142 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); in jpeg_v5_0_2_sw_init()
155 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v5_0_2_sw_init()
158 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v5_0_2_sw_init()
159 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v5_0_2_sw_init()
161 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); in jpeg_v5_0_2_sw_init()
165 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); in jpeg_v5_0_2_sw_init()
166 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v5_0_2_sw_init()
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H A Djpeg_v2_5.c79 adev->jpeg.num_jpeg_rings = 1; in jpeg_v2_5_early_init()
80 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS; in jpeg_v2_5_early_init()
81 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in jpeg_v2_5_early_init()
84 adev->jpeg.harvest_config |= 1 << i; in jpeg_v2_5_early_init()
86 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 | in jpeg_v2_5_early_init()
110 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_sw_init()
111 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_sw_init()
116 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); in jpeg_v2_5_sw_init()
122 VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); in jpeg_v2_5_sw_init()
128 VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); in jpeg_v2_5_sw_init()
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H A Djpeg_v5_0_1.c118 if (!adev->jpeg.num_jpeg_inst || adev->jpeg.num_jpeg_inst > AMDGPU_MAX_JPEG_INSTANCES) in jpeg_v5_0_1_early_init()
121 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; in jpeg_v5_0_1_early_init()
142 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v5_0_1_sw_init()
145 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); in jpeg_v5_0_1_sw_init()
151 VCN_5_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v5_0_1_sw_init()
157 VCN_5_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v5_0_1_sw_init()
169 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v5_0_1_sw_init()
172 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v5_0_1_sw_init()
173 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v5_0_1_sw_init()
175 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); in jpeg_v5_0_1_sw_init()
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H A Djpeg_v4_0_5.c91 adev->jpeg.num_jpeg_inst = 1; in jpeg_v4_0_5_early_init()
94 adev->jpeg.num_jpeg_inst = 2; in jpeg_v4_0_5_early_init()
103 adev->jpeg.num_jpeg_rings = 1; in jpeg_v4_0_5_early_init()
124 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_sw_init()
125 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_sw_init()
130 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
136 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
142 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
155 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_sw_init()
156 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_sw_init()
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H A Djpeg_v4_0_3.c100 return (adev->jpeg.caps & AMDGPU_JPEG_CAPS(RRMT_ENABLED)) == 0; in jpeg_v4_0_3_normalizn_reqd()
122 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; in jpeg_v4_0_3_early_init()
144 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
147 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); in jpeg_v4_0_3_sw_init()
154 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v4_0_3_sw_init()
160 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v4_0_3_sw_init()
172 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_sw_init()
175 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
176 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v4_0_3_sw_init()
178 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); in jpeg_v4_0_3_sw_init()
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H A Djpeg_v5_3_0.c54 adev->jpeg.num_jpeg_inst = 1; in jpeg_v5_3_0_early_init()
55 adev->jpeg.num_jpeg_rings = 1; in jpeg_v5_3_0_early_init()
78 VCN_5_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v5_3_0_sw_init()
90 ring = adev->jpeg.inst->ring_dec; in jpeg_v5_3_0_sw_init()
96 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v5_3_0_sw_init()
101 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v5_3_0_sw_init()
102 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); in jpeg_v5_3_0_sw_init()
105 adev->jpeg.supported_reset = in jpeg_v5_3_0_sw_init()
106 amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); in jpeg_v5_3_0_sw_init()
108 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v5_3_0_sw_init()
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H A Djpeg_v5_0_0.c69 adev->jpeg.num_jpeg_inst = 1; in jpeg_v5_0_0_early_init()
70 adev->jpeg.num_jpeg_rings = 1; in jpeg_v5_0_0_early_init()
93 VCN_5_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v5_0_0_sw_init()
105 ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_sw_init()
111 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v5_0_0_sw_init()
116 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v5_0_0_sw_init()
117 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); in jpeg_v5_0_0_sw_init()
123 adev->jpeg.supported_reset = in jpeg_v5_0_0_sw_init()
124 amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); in jpeg_v5_0_0_sw_init()
126 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v5_0_0_sw_init()
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H A Djpeg_v4_0.c75 adev->jpeg.num_jpeg_inst = 1; in jpeg_v4_0_early_init()
76 adev->jpeg.num_jpeg_rings = 1; in jpeg_v4_0_early_init()
100 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v4_0_sw_init()
106 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v4_0_sw_init()
112 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v4_0_sw_init()
124 ring = adev->jpeg.inst->ring_dec; in jpeg_v4_0_sw_init()
130 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v4_0_sw_init()
135 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v4_0_sw_init()
136 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); in jpeg_v4_0_sw_init()
146 adev->jpeg.supported_reset = in jpeg_v4_0_sw_init()
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H A Djpeg_v3_0.c82 adev->jpeg.num_jpeg_inst = 1; in jpeg_v3_0_early_init()
83 adev->jpeg.num_jpeg_rings = 1; in jpeg_v3_0_early_init()
106 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v3_0_sw_init()
118 ring = adev->jpeg.inst->ring_dec; in jpeg_v3_0_sw_init()
123 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v3_0_sw_init()
128 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v3_0_sw_init()
129 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); in jpeg_v3_0_sw_init()
135 adev->jpeg.supported_reset = in jpeg_v3_0_sw_init()
136 amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec); in jpeg_v3_0_sw_init()
138 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v3_0_sw_init()
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H A Djpeg_v2_0.c67 adev->jpeg.num_jpeg_inst = 1; in jpeg_v2_0_early_init()
68 adev->jpeg.num_jpeg_rings = 1; in jpeg_v2_0_early_init()
91 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v2_0_sw_init()
103 ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_sw_init()
108 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, in jpeg_v2_0_sw_init()
113 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v2_0_sw_init()
114 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); in jpeg_v2_0_sw_init()
120 adev->jpeg.supported_reset = in jpeg_v2_0_sw_init()
121 amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec); in jpeg_v2_0_sw_init()
123 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v2_0_sw_init()
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/linux/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-core.c590 switch (ctx->jpeg->variant->version) { in s5p_jpeg_to_user_subsampling()
767 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_parse_decode_h_tbl() local
799 exynos4_jpeg_select_dec_h_tbl(jpeg->regs, c, in exynos4_jpeg_parse_decode_h_tbl()
807 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_parse_huff_tbl() local
835 writel(word, jpeg->regs + in exynos4_jpeg_parse_huff_tbl()
849 writel(word, jpeg->regs + in exynos4_jpeg_parse_huff_tbl()
856 writel(word, jpeg->regs + in exynos4_jpeg_parse_huff_tbl()
866 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_parse_decode_q_tbl() local
881 exynos4_jpeg_set_dec_components(jpeg->regs, components); in exynos4_jpeg_parse_decode_q_tbl()
891 exynos4_jpeg_select_dec_q_tbl(jpeg->regs, c, x); in exynos4_jpeg_parse_decode_q_tbl()
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H A DMakefile2 s5p-jpeg-objs := jpeg-core.o jpeg-hw-exynos3250.o jpeg-hw-exynos4.o jpeg-hw-s5p.o
3 obj-$(CONFIG_VIDEO_SAMSUNG_S5P_JPEG) += s5p-jpeg.o
/linux/drivers/media/platform/nxp/imx-jpeg/
H A DMakefile2 mxc-jpeg-encdec-objs := mxc-jpeg-hw.o mxc-jpeg.o
3 obj-$(CONFIG_VIDEO_IMX8_JPEG) += mxc-jpeg-encdec.o
/linux/drivers/media/platform/mediatek/jpeg/
H A DMakefile3 mtk-jpeg-enc-hw.o \
4 mtk-jpeg-dec-hw.o
9 mtk-jpeg-enc-hw-y := mtk_jpeg_enc_hw.o
10 mtk-jpeg-dec-hw-y := mtk_jpeg_dec_hw.o
H A DKconfig12 Mediatek jpeg codec driver provides HW capability to decode
16 module will be called mtk-jpeg
/linux/drivers/media/platform/imagination/
H A DMakefile2 e5010_jpeg_enc-objs := e5010-jpeg-enc-hw.o e5010-jpeg-enc.o
/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-g-jpegcomp.rst39 :ref:`JPEG class controls <jpeg-controls>` for image quality and JPEG
69 :ref:`V4L2_CID_JPEG_COMPRESSION_QUALITY <jpeg-quality-control>`
89 - See :ref:`jpeg-markers`. Deprecated. If
90 :ref:`V4L2_CID_JPEG_ACTIVE_MARKER <jpeg-active-marker-control>`
/linux/Documentation/driver-api/media/
H A Dv4l2-jpeg.rst6 .. kernel-doc:: include/media/v4l2-jpeg.h
9 .. kernel-doc:: drivers/media/v4l2-core/v4l2-jpeg.c
/linux/drivers/media/platform/mediatek/
H A DMakefile2 obj-y += jpeg/
H A DKconfig5 source "drivers/media/platform/mediatek/jpeg/Kconfig"
/linux/drivers/media/platform/samsung/
H A DMakefile6 obj-y += s5p-jpeg/
H A DKconfig9 source "drivers/media/platform/samsung/s5p-jpeg/Kconfig"
/linux/drivers/media/platform/chips-media/coda/
H A DMakefile3 …a-vpu-objs := coda-common.o coda-bit.o coda-gdi.o coda-h264.o coda-mpeg2.o coda-mpeg4.o coda-jpeg.o
/linux/drivers/media/platform/nxp/
H A DMakefile4 obj-y += imx-jpeg/

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