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Searched refs:ixSQ_WAVE_TTMP10 (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h96 #define ixSQ_WAVE_TTMP10 0x027A macro
H A Dgfx_7_0_d.h1935 #define ixSQ_WAVE_TTMP10 0x27a macro
H A Dgfx_7_2_d.h1956 #define ixSQ_WAVE_TTMP10 0x27a macro
H A Dgfx_8_1_d.h2123 #define ixSQ_WAVE_TTMP10 0x27a macro
H A Dgfx_8_0_d.h2155 #define ixSQ_WAVE_TTMP10 0x27a macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h7121 #define ixSQ_WAVE_TTMP10 … macro
H A Dgc_9_4_3_offset.h7431 #define ixSQ_WAVE_TTMP10 … macro
H A Dgc_9_1_offset.h7329 #define ixSQ_WAVE_TTMP10 … macro
H A Dgc_9_4_2_offset.h7668 #define ixSQ_WAVE_TTMP10 … macro
H A Dgc_9_2_1_offset.h7368 #define ixSQ_WAVE_TTMP10 … macro
H A Dgc_11_5_0_offset.h9989 #define ixSQ_WAVE_TTMP10 … macro
H A Dgc_10_1_0_offset.h11216 #define ixSQ_WAVE_TTMP10 … macro
H A Dgc_12_0_0_offset.h11044 #define ixSQ_WAVE_TTMP10 … macro
H A Dgc_11_0_3_offset.h12082 #define ixSQ_WAVE_TTMP10 … macro
H A Dgc_11_0_0_offset.h11674 #define ixSQ_WAVE_TTMP10 … macro
H A Dgc_10_3_0_offset.h13453 #define ixSQ_WAVE_TTMP10 … macro