Home
last modified time | relevance | path

Searched refs:ixSQ_WAVE_INST_DW0 (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h82 #define ixSQ_WAVE_INST_DW0 0x001A macro
H A Dgfx_7_0_d.h1906 #define ixSQ_WAVE_INST_DW0 0x1a macro
H A Dgfx_7_2_d.h1927 #define ixSQ_WAVE_INST_DW0 0x1a macro
H A Dgfx_8_1_d.h2093 #define ixSQ_WAVE_INST_DW0 0x1a macro
H A Dgfx_8_0_d.h2125 #define ixSQ_WAVE_INST_DW0 0x1a macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_2.c1840 wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v9_4_2_log_cu_timeout_status()
H A Dgfx_v6_0.c2984 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v6_0_read_wave_data()
H A Dgfx_v7_0.c4090 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v7_0_read_wave_data()
H A Dgfx_v9_4_3.c772 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v9_4_3_read_wave_data()
H A Dgfx_v8_0.c5246 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v8_0_read_wave_data()
H A Dgfx_v9_0.c1963 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v9_0_read_wave_data()
H A Dgfx_v10_0.c4461 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); in gfx_v10_0_read_wave_data()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h7106 #define ixSQ_WAVE_INST_DW0 macro
H A Dgc_9_4_3_offset.h7416 #define ixSQ_WAVE_INST_DW0 macro
H A Dgc_9_1_offset.h7314 #define ixSQ_WAVE_INST_DW0 macro
H A Dgc_9_4_2_offset.h7654 #define ixSQ_WAVE_INST_DW0 macro
H A Dgc_9_2_1_offset.h7353 #define ixSQ_WAVE_INST_DW0 macro
H A Dgc_10_1_0_offset.h11197 #define ixSQ_WAVE_INST_DW0 macro
H A Dgc_10_3_0_offset.h13431 #define ixSQ_WAVE_INST_DW0 macro