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Searched refs:ixSQ_WAVE_EXEC_HI (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h76 #define ixSQ_WAVE_EXEC_HI 0x027F macro
H A Dgfx_7_0_d.h1912 #define ixSQ_WAVE_EXEC_HI 0x27f macro
H A Dgfx_7_2_d.h1933 #define ixSQ_WAVE_EXEC_HI 0x27f macro
H A Dgfx_8_1_d.h2100 #define ixSQ_WAVE_EXEC_HI 0x27f macro
H A Dgfx_8_0_d.h2132 #define ixSQ_WAVE_EXEC_HI 0x27f macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_2.c1838 wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_4_2_log_cu_timeout_status()
H A Dgfx_v7_0.c4082 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
H A Dgfx_v12_0.c813 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v12_0_read_wave_data()
H A Dgfx_v8_0.c5230 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
H A Dgfx_v11_0.c988 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v11_0_read_wave_data()
H A Dgfx_v9_0.c1951 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
H A Dgfx_v10_0.c4452 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v10_0_read_wave_data()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h7129 #define ixSQ_WAVE_EXEC_HI macro
H A Dgc_9_4_3_offset.h7439 #define ixSQ_WAVE_EXEC_HI macro
H A Dgc_9_1_offset.h7337 #define ixSQ_WAVE_EXEC_HI macro
H A Dgc_9_4_2_offset.h7676 #define ixSQ_WAVE_EXEC_HI macro
H A Dgc_9_2_1_offset.h7376 #define ixSQ_WAVE_EXEC_HI macro
H A Dgc_11_5_0_offset.h9997 #define ixSQ_WAVE_EXEC_HI macro
H A Dgc_10_1_0_offset.h11224 #define ixSQ_WAVE_EXEC_HI macro
H A Dgc_12_0_0_offset.h11052 #define ixSQ_WAVE_EXEC_HI macro
H A Dgc_11_0_3_offset.h12090 #define ixSQ_WAVE_EXEC_HI macro
H A Dgc_11_0_0_offset.h11682 #define ixSQ_WAVE_EXEC_HI macro
H A Dgc_10_3_0_offset.h13461 #define ixSQ_WAVE_EXEC_HI macro