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Searched refs:ixGRA05 (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h306 #define ixGRA05 0x0005 macro
H A Ddce_8_0_d.h5105 #define ixGRA05 0x5 macro
H A Ddce_10_0_d.h5988 #define ixGRA05 0x5 macro
H A Ddce_11_0_d.h6065 #define ixGRA05 0x5 macro
H A Ddce_11_2_d.h7739 #define ixGRA05 0x5 macro
H A Ddce_12_0_offset.h18178 #define ixGRA05 … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7271 #define ixGRA05 … macro
H A Ddcn_3_0_1_offset.h12070 #define ixGRA05 … macro
H A Ddcn_1_0_offset.h12809 #define ixGRA05 … macro
H A Ddcn_2_1_0_offset.h12674 #define ixGRA05 … macro
H A Ddcn_3_2_0_offset.h13441 #define ixGRA05 … macro
H A Ddcn_3_1_5_offset.h13994 #define ixGRA05 … macro
H A Ddcn_3_1_4_offset.h120 #define ixGRA05 … macro
H A Ddcn_3_1_2_offset.h13888 #define ixGRA05 … macro
H A Ddcn_3_2_1_offset.h13395 #define ixGRA05 … macro
H A Ddcn_3_1_6_offset.h14485 #define ixGRA05 … macro
H A Ddcn_3_0_2_offset.h15073 #define ixGRA05 … macro
H A Ddcn_2_0_0_offset.h16338 #define ixGRA05 … macro
H A Ddcn_3_0_0_offset.h16823 #define ixGRA05 … macro