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Searched refs:ixDIDT_TD_EDC_CTRL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_powertune.c543 …{ ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_EN_MASK, DIDT_T…
544 …{ ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK, DIDT_T…
545 …{ ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_T…
546 …{ ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_T…
547 …{ ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_T…
548 …{ ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_T…
549 …{ ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_T…
550 …{ ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK, DIDT_T…
551 …{ ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_T…
552 …{ ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_T…
[all …]
H A Dsmu7_hwmgr.c123 #define ixDIDT_TD_EDC_CTRL 0x0053 macro
156 ixDIDT_TD_EDC_CTRL,
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h7207 #define ixDIDT_TD_EDC_CTRL … macro
H A Dgc_9_1_offset.h7414 #define ixDIDT_TD_EDC_CTRL … macro
H A Dgc_9_4_2_offset.h104 #define ixDIDT_TD_EDC_CTRL … macro
H A Dgc_9_2_1_offset.h7455 #define ixDIDT_TD_EDC_CTRL … macro
H A Dgc_10_1_0_offset.h11320 #define ixDIDT_TD_EDC_CTRL … macro
H A Dgc_10_3_0_offset.h13554 #define ixDIDT_TD_EDC_CTRL … macro