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Searched refs:ixDIDT_SQ_EDC_STALL_PATTERN_5_6 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_powertune.c403 …{ ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, …
432 …{ ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, …
597 …{ ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK, D…
598 …{ ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK, D…
H A Dsmu7_hwmgr.c120 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 macro
147 ixDIDT_SQ_EDC_STALL_PATTERN_5_6,
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h7160 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 … macro
H A Dgc_9_1_offset.h7368 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 … macro
H A Dgc_9_4_2_offset.h51 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 … macro
H A Dgc_9_2_1_offset.h7410 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 … macro
H A Dgc_10_1_0_offset.h11258 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 … macro
H A Dgc_10_3_0_offset.h13492 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 … macro