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Searched refs:ixDIDT_DB_CTRL0 (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_powertune.c241 …{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_CTRL…
242 …{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__PHASE_OFFSET_MASK, DIDT_DB_CTRL0__PHASE_OFF…
243 …{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK, DIDT_DB_CTRL0__DIDT_CTR…
244 …{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL0__D…
245 …{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_DB_CTRL0__DID…
246 …{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_DB_CTRL0__DI…
247 …{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_DB_CT…
248 …{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_DB_CTRL0…
249 …{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_DB_CTRL0__DIDT_…
250 …{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_DB_CTRL0__DI…
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h2513 #define ixDIDT_DB_CTRL0 0x20 macro
H A Dgfx_7_2_d.h2538 #define ixDIDT_DB_CTRL0 0x20 macro
H A Dgfx_8_1_d.h2762 #define ixDIDT_DB_CTRL0 0x20 macro
H A Dgfx_8_0_d.h2784 #define ixDIDT_DB_CTRL0 0x20 macro
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dkv_dpm.c464 data = RREG32_DIDT(ixDIDT_DB_CTRL0); in kv_do_enable_didt()
469 WREG32_DIDT(ixDIDT_DB_CTRL0, data); in kv_do_enable_didt()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h7169 #define ixDIDT_DB_CTRL0 … macro
H A Dgc_9_1_offset.h7376 #define ixDIDT_DB_CTRL0 … macro
H A Dgc_9_4_2_offset.h60 #define ixDIDT_DB_CTRL0 … macro
H A Dgc_9_2_1_offset.h7414 #define ixDIDT_DB_CTRL0 … macro
H A Dgc_10_1_0_offset.h11269 #define ixDIDT_DB_CTRL0 … macro
H A Dgc_10_3_0_offset.h13503 #define ixDIDT_DB_CTRL0 … macro