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Searched refs:ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7560 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_0_1_offset.h12359 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_1_0_offset.h13203 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_2_1_0_offset.h12963 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_2_0_offset.h13730 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_1_5_offset.h14283 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_5_1_offset.h206 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_5_0_offset.h227 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_1_4_offset.h274 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_1_2_offset.h14177 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_2_1_offset.h13684 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_1_6_offset.h14774 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_0_2_offset.h15362 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_4_1_0_offset.h15740 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_2_0_0_offset.h16627 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_0_0_offset.h17111 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h17016 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro