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Searched refs:ixAZALIA_CRC1_CHANNEL5 (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_d.h5468 #define ixAZALIA_CRC1_CHANNEL5 0x5 macro
H A Ddce_10_0_d.h6739 #define ixAZALIA_CRC1_CHANNEL5 0x5 macro
H A Ddce_11_0_d.h6901 #define ixAZALIA_CRC1_CHANNEL5 0x5 macro
H A Ddce_11_2_d.h8246 #define ixAZALIA_CRC1_CHANNEL5 0x5 macro
H A Ddce_12_0_offset.h18125 #define ixAZALIA_CRC1_CHANNEL5 … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7452 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_3_0_1_offset.h12251 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_1_0_offset.h13095 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_2_1_0_offset.h12855 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_3_2_0_offset.h13622 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_3_1_5_offset.h14175 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_3_5_1_offset.h153 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_3_5_0_offset.h174 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_3_1_4_offset.h221 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_3_1_2_offset.h14069 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_3_2_1_offset.h13576 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_3_1_6_offset.h14666 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_3_0_2_offset.h15254 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_4_1_0_offset.h15632 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_2_0_0_offset.h16519 #define ixAZALIA_CRC1_CHANNEL5 … macro
H A Ddcn_3_0_0_offset.h17004 #define ixAZALIA_CRC1_CHANNEL5 … macro