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Searched refs:ixAZALIA_CRC0_CHANNEL5 (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_d.h5455 #define ixAZALIA_CRC0_CHANNEL5 0x5 macro
H A Ddce_10_0_d.h6726 #define ixAZALIA_CRC0_CHANNEL5 0x5 macro
H A Ddce_11_0_d.h6888 #define ixAZALIA_CRC0_CHANNEL5 0x5 macro
H A Ddce_11_2_d.h8233 #define ixAZALIA_CRC0_CHANNEL5 0x5 macro
H A Ddce_12_0_offset.h18113 #define ixAZALIA_CRC0_CHANNEL5 … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7440 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_3_0_1_offset.h12239 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_1_0_offset.h13083 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_2_1_0_offset.h12843 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_3_2_0_offset.h13610 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_3_1_5_offset.h14163 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_3_5_1_offset.h141 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_3_5_0_offset.h162 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_3_1_4_offset.h209 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_3_1_2_offset.h14057 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_3_2_1_offset.h13564 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_3_1_6_offset.h14654 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_3_0_2_offset.h15242 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_4_1_0_offset.h15620 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_2_0_0_offset.h16507 #define ixAZALIA_CRC0_CHANNEL5 … macro
H A Ddcn_3_0_0_offset.h16992 #define ixAZALIA_CRC0_CHANNEL5 … macro