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Searched refs:ix (Results 1 – 25 of 54) sorted by relevance

123

/linux/arch/sh/kernel/cpu/sh2a/
H A Dfpu.c96 unsigned int ix, iy; in denormal_mulf() local
100 ix = hx & 0x7fffffff; in denormal_mulf()
102 if (iy < 0x00800000 || ix == 0) in denormal_mulf()
106 ix &= 0x007fffff; in denormal_mulf()
108 m = (unsigned long long)ix * iy; in denormal_mulf()
116 ix = ((int) (m >> (w - 23)) & 0x007fffff) | (exp << 23); in denormal_mulf()
118 ix = (int) (m >> (w - 22 - exp)) & 0x007fffff; in denormal_mulf()
120 ix = 0; in denormal_mulf()
122 ix |= (hx ^ hy) & 0x80000000; in denormal_mulf()
123 return ix; in denormal_mulf()
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/linux/io_uring/
H A Dxattr.c27 struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); in io_xattr_cleanup() local
29 dismiss_delayed_filename(&ix->filename); in io_xattr_cleanup()
30 kfree(ix->ctx.kname); in io_xattr_cleanup()
31 kvfree(ix->ctx.kvalue); in io_xattr_cleanup()
45 struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); in __io_getxattr_prep() local
49 INIT_DELAYED_FILENAME(&ix->filename); in __io_getxattr_prep()
50 ix->ctx.kvalue = NULL; in __io_getxattr_prep()
52 ix->ctx.value = u64_to_user_ptr(READ_ONCE(sqe->addr2)); in __io_getxattr_prep()
53 ix->ctx.size = READ_ONCE(sqe->len); in __io_getxattr_prep()
54 ix->ctx.flags = READ_ONCE(sqe->xattr_flags); in __io_getxattr_prep()
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/linux/arch/mips/math-emu/
H A Dsp_sqrt.c14 int ix, s, q, m, t, i; in ieee754sp_sqrt() local
56 ix = x.bits; in ieee754sp_sqrt()
59 m = (ix >> 23); in ieee754sp_sqrt()
61 for (i = 0; (ix & 0x00800000) == 0; i++) in ieee754sp_sqrt()
62 ix <<= 1; in ieee754sp_sqrt()
66 ix = (ix & 0x007fffff) | 0x00800000; in ieee754sp_sqrt()
68 ix += ix; in ieee754sp_sqrt()
72 ix += ix; in ieee754sp_sqrt()
79 if (t <= ix) { in ieee754sp_sqrt()
81 ix -= t; in ieee754sp_sqrt()
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/linux/net/rxrpc/
H A Dinput_rack.c24 struct rxrpc_txqueue *tq, unsigned int ix) in rxrpc_rack_mark_lost() argument
26 if (__test_and_set_bit(ix, &tq->segment_lost)) { in rxrpc_rack_mark_lost()
27 if (__test_and_clear_bit(ix, &tq->segment_retransmitted)) in rxrpc_rack_mark_lost()
32 tq->segment_xmit_ts[ix] = UINT_MAX; in rxrpc_rack_mark_lost()
38 static ktime_t rxrpc_get_xmit_ts(const struct rxrpc_txqueue *tq, unsigned int ix) in rxrpc_get_xmit_ts() argument
40 if (tq->segment_xmit_ts[ix] == UINT_MAX) in rxrpc_get_xmit_ts()
42 return ktime_add_us(tq->xmit_ts_base, tq->segment_xmit_ts[ix]); in rxrpc_get_xmit_ts()
65 unsigned int ix) in rxrpc_rack_update() argument
67 rxrpc_seq_t seq = tq->qbase + ix; in rxrpc_rack_update()
68 ktime_t xmit_ts = rxrpc_get_xmit_ts(tq, ix); in rxrpc_rack_update()
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H A Dcall_event.c64 unsigned int ix = req->seq & RXRPC_TXQ_MASK; in rxrpc_retransmit_data() local
65 struct rxrpc_txbuf *txb = tq->bufs[ix]; in rxrpc_retransmit_data()
67 _enter("%x,%x,%x,%x", tq->qbase, req->seq, ix, txb->debug_id); in rxrpc_retransmit_data()
111 unsigned int ix = __ffs(lost); in rxrpc_resend() local
112 struct rxrpc_txbuf *txb = tq->bufs[ix]; in rxrpc_resend()
114 __clear_bit(ix, &lost); in rxrpc_resend()
118 req.seq = tq->qbase + ix; in rxrpc_resend()
231 int ix; in rxrpc_transmit_fresh_data() local
234 ix = seq & RXRPC_TXQ_MASK; in rxrpc_transmit_fresh_data()
235 if (!ix) { in rxrpc_transmit_fresh_data()
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H A Dinput.c208 int ix) in rxrpc_add_data_rtt_sample()
210 ktime_t xmit_ts = ktime_add_us(tq->xmit_ts_base, tq->segment_xmit_ts[ix]); in rxrpc_add_data_rtt_sample()
215 __clear_bit(ix, &tq->rtt_samples); /* Prevent repeat RTT sample */ in rxrpc_add_data_rtt_sample()
255 unsigned int ix = seq - call->tx_qbase; in rxrpc_rotate_tx_window()
257 _debug("tq=%x seq=%x i=%d f=%x", tq->qbase, seq, ix, tq->bufs[ix]->flags); in rxrpc_rotate_tx_window()
258 if (tq->bufs[ix]->flags & RXRPC_LAST_PACKET) { in rxrpc_rotate_tx_window()
263 if (summary->acked_serial == tq->segment_serial[ix] && in rxrpc_rotate_tx_window()
264 test_bit(ix, &tq->rtt_samples)) in rxrpc_rotate_tx_window()
265 rxrpc_add_data_rtt_sample(call, summary, tq, ix); in rxrpc_rotate_tx_window()
207 rxrpc_add_data_rtt_sample(struct rxrpc_call * call,struct rxrpc_ack_summary * summary,struct rxrpc_txqueue * tq,int ix) rxrpc_add_data_rtt_sample() argument
251 unsigned int ix = seq - call->tx_qbase; rxrpc_rotate_tx_window() local
861 for (int ix = 0; ix < RXRPC_NR_TXQUEUE; ix++) rxrpc_input_soft_rtt() local
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/linux/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Dchannels.c14 static struct mlx5e_channel *mlx5e_channels_get(struct mlx5e_channels *chs, unsigned int ix) in mlx5e_channels_get() argument
16 WARN_ON_ONCE(ix >= mlx5e_channels_get_num(chs)); in mlx5e_channels_get()
17 return chs->c[ix]; in mlx5e_channels_get()
20 bool mlx5e_channels_is_xsk(struct mlx5e_channels *chs, unsigned int ix) in mlx5e_channels_is_xsk() argument
22 struct mlx5e_channel *c = mlx5e_channels_get(chs, ix); in mlx5e_channels_is_xsk()
27 void mlx5e_channels_get_regular_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn, in mlx5e_channels_get_regular_rqn() argument
30 struct mlx5e_channel *c = mlx5e_channels_get(chs, ix); in mlx5e_channels_get_regular_rqn()
37 void mlx5e_channels_get_xsk_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn, in mlx5e_channels_get_xsk_rqn() argument
40 struct mlx5e_channel *c = mlx5e_channels_get(chs, ix); in mlx5e_channels_get_xsk_rqn()
H A Dchannels.h12 bool mlx5e_channels_is_xsk(struct mlx5e_channels *chs, unsigned int ix);
13 void mlx5e_channels_get_regular_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn,
15 void mlx5e_channels_get_xsk_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn,
H A Dfs_tt_redirect.c148 int ix = 0; in fs_udp_create_groups() local
178 MLX5_SET_CFG(in, start_flow_index, ix); in fs_udp_create_groups()
179 ix += MLX5E_FS_UDP_GROUP1_SIZE; in fs_udp_create_groups()
180 MLX5_SET_CFG(in, end_flow_index, ix - 1); in fs_udp_create_groups()
188 MLX5_SET_CFG(in, start_flow_index, ix); in fs_udp_create_groups()
189 ix += MLX5E_FS_UDP_GROUP2_SIZE; in fs_udp_create_groups()
190 MLX5_SET_CFG(in, end_flow_index, ix - 1); in fs_udp_create_groups()
430 int ix = 0; in fs_any_create_groups() local
449 MLX5_SET_CFG(in, start_flow_index, ix); in fs_any_create_groups()
450 ix += MLX5E_FS_ANY_GROUP1_SIZE; in fs_any_create_groups()
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H A Dqos.c59 int ix; in mlx5e_get_qos_sq() local
61 ix = qid % params->num_channels; in mlx5e_get_qos_sq()
63 c = priv->channels.c[ix]; in mlx5e_get_qos_sq()
76 int txq_ix, ix, qid, err = 0; in mlx5e_open_qos_sq() local
112 ix = node_qid % params->num_channels; in mlx5e_open_qos_sq()
114 c = chs->c[ix]; in mlx5e_open_qos_sq()
217 int ix; in mlx5e_close_qos_sq() local
221 ix = qid % params->num_channels; in mlx5e_close_qos_sq()
223 c = priv->channels.c[ix]; in mlx5e_close_qos_sq()
341 u16 qid = params->num_channels * i + c->ix; in mlx5e_qos_deactivate_queues()
/linux/fs/netfs/
H A Diterator.c128 unsigned int nbv = iter->nr_segs, ix = 0, nsegs = 0; in netfs_limit_bvec() local
137 while (n && ix < nbv && skip) { in netfs_limit_bvec()
138 len = bvecs[ix].bv_len; in netfs_limit_bvec()
143 ix++; in netfs_limit_bvec()
146 while (n && ix < nbv) { in netfs_limit_bvec()
147 len = min3(n, bvecs[ix].bv_len - skip, max_size); in netfs_limit_bvec()
150 ix++; in netfs_limit_bvec()
169 unsigned int nkv = iter->nr_segs, ix = 0, nsegs = 0; in netfs_limit_kvec() local
178 while (n && ix < nkv && skip) { in netfs_limit_kvec()
179 len = kvecs[ix].iov_len; in netfs_limit_kvec()
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H A Drolling_buffer.c122 int nr, ix, to; in rolling_buffer_load_from_ra() local
132 ix = fq->vec.nr; in rolling_buffer_load_from_ra()
133 to = ix + nr; in rolling_buffer_load_from_ra()
135 for (; ix < to; ix++) { in rolling_buffer_load_from_ra()
136 struct folio *folio = folioq_folio(fq, ix); in rolling_buffer_load_from_ra()
139 fq->orders[ix] = order; in rolling_buffer_load_from_ra()
/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dfs_ttc.c467 int ix = *next_ix; in mlx5_create_ttc_table_ipsec_groups() local
474 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_ipsec_groups()
475 ix += groups->group_size[ttc->num_groups]; in mlx5_create_ttc_table_ipsec_groups()
476 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5_create_ttc_table_ipsec_groups()
492 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_ipsec_groups()
493 ix += groups->group_size[ttc->num_groups]; in mlx5_create_ttc_table_ipsec_groups()
494 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5_create_ttc_table_ipsec_groups()
513 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_ipsec_groups()
514 ix += groups->group_size[ttc->num_groups]; in mlx5_create_ttc_table_ipsec_groups()
515 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5_create_ttc_table_ipsec_groups()
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H A Dmpfs.h57 int ix = MLX5_L2_ADDR_HASH(mac); \
61 hlist_for_each_entry(ptr, &(hash)[ix], node.hlist) \
72 int ix = MLX5_L2_ADDR_HASH(mac); \
78 hlist_add_head(&ptr->node.hlist, &(hash)[ix]);\
H A Dmpfs.c80 static int alloc_l2table_index(struct mlx5_mpfs *l2table, u32 *ix) in alloc_l2table_index() argument
84 *ix = find_first_zero_bit(l2table->bitmap, l2table->size); in alloc_l2table_index()
85 if (*ix >= l2table->size) in alloc_l2table_index()
88 __set_bit(*ix, l2table->bitmap); in alloc_l2table_index()
93 static void free_l2table_index(struct mlx5_mpfs *l2table, u32 ix) in free_l2table_index() argument
95 __clear_bit(ix, l2table->bitmap); in free_l2table_index()
/linux/arch/s390/lib/
H A Dspinlock.c83 int ix; in arch_spin_lock_setup() local
86 for (ix = 0; ix < 4; ix++, node++) { in arch_spin_lock_setup()
89 (ix << _Q_TAIL_IDX_OFFSET); in arch_spin_lock_setup()
138 int ix, cpu; in arch_spin_decode_tail() local
140 ix = (lock & _Q_TAIL_IDX_MASK) >> _Q_TAIL_IDX_OFFSET; in arch_spin_decode_tail()
142 return per_cpu_ptr(&spin_wait[ix], cpu - 1); in arch_spin_decode_tail()
159 int lockval, ix, node_id, tail_id, old, new, owner, count; in arch_spin_lock_queued() local
161 ix = get_lowcore()->spinlock_index++; in arch_spin_lock_queued()
164 node = this_cpu_ptr(&spin_wait[ix]); in arch_spin_lock_queued()
/linux/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/
H A Dpool.h10 struct mlx5e_xsk *xsk, u16 ix) in mlx5e_xsk_get_pool() argument
15 if (unlikely(ix >= params->num_channels)) in mlx5e_xsk_get_pool()
18 return xsk->pools[ix]; in mlx5e_xsk_get_pool()
H A Drx.h11 int mlx5e_xsk_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
12 int mlx5e_xsk_alloc_rx_wqes_batched(struct mlx5e_rq *rq, u16 ix, int wqe_bulk);
13 int mlx5e_xsk_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, int wqe_bulk);
/linux/fs/ext4/
H A Dext4_extents.h232 static inline ext4_fsblk_t ext4_idx_pblock(struct ext4_extent_idx *ix) in ext4_idx_pblock() argument
236 block = le32_to_cpu(ix->ei_leaf_lo); in ext4_idx_pblock()
237 block |= ((ext4_fsblk_t) le16_to_cpu(ix->ei_leaf_hi) << 31) << 1; in ext4_idx_pblock()
259 static inline void ext4_idx_store_pblock(struct ext4_extent_idx *ix, in ext4_idx_store_pblock() argument
262 ix->ei_leaf_lo = cpu_to_le32((unsigned long) (pb & 0xffffffff)); in ext4_idx_store_pblock()
263 ix->ei_leaf_hi = cpu_to_le16((unsigned long) ((pb >> 31) >> 1) & in ext4_idx_store_pblock()
/linux/drivers/net/ethernet/mellanox/mlx5/core/fpga/
H A Dconn.c103 unsigned int ix; in mlx5_fpga_conn_post_recv() local
115 ix = conn->qp.rq.pc & (conn->qp.rq.size - 1); in mlx5_fpga_conn_post_recv()
116 data = mlx5_wq_cyc_get_wqe(&conn->qp.wq.rq, ix); in mlx5_fpga_conn_post_recv()
122 conn->qp.rq.bufs[ix] = buf; in mlx5_fpga_conn_post_recv()
146 unsigned int ix, sgi; in mlx5_fpga_conn_post_send() local
149 ix = conn->qp.sq.pc & (conn->qp.sq.size - 1); in mlx5_fpga_conn_post_send()
151 ctrl = mlx5_wq_cyc_get_wqe(&conn->qp.wq.sq, ix); in mlx5_fpga_conn_post_send()
171 conn->qp.sq.bufs[ix] = buf; in mlx5_fpga_conn_post_send()
254 int ix, err; in mlx5_fpga_conn_rq_cqe() local
256 ix = be16_to_cpu(cqe->wqe_counter) & (conn->qp.rq.size - 1); in mlx5_fpga_conn_rq_cqe()
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/linux/drivers/net/wireless/marvell/mwifiex/
H A Dutil.c801 int ix; in mwifiex_hist_data_reset() local
805 for (ix = 0; ix < MWIFIEX_MAX_AC_RX_RATES; ix++) in mwifiex_hist_data_reset()
806 atomic_set(&phist_data->rx_rate[ix], 0); in mwifiex_hist_data_reset()
807 for (ix = 0; ix < MWIFIEX_MAX_SNR; ix++) in mwifiex_hist_data_reset()
808 atomic_set(&phist_data->snr[ix], 0); in mwifiex_hist_data_reset()
809 for (ix = 0; ix < MWIFIEX_MAX_NOISE_FLR; ix++) in mwifiex_hist_data_reset()
810 atomic_set(&phist_data->noise_flr[ix], 0); in mwifiex_hist_data_reset()
811 for (ix = 0; ix < MWIFIEX_MAX_SIG_STRENGTH; ix++) in mwifiex_hist_data_reset()
812 atomic_set(&phist_data->sig_str[ix], 0); in mwifiex_hist_data_reset()
/linux/drivers/gpu/drm/radeon/
H A Dtrinity_dpm.c541 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_divider_value() local
548 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_divider_value()
551 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_divider_value()
558 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix); in trinity_set_divider_value()
561 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value); in trinity_set_divider_value()
568 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_ds_dividers() local
570 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ds_dividers()
573 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ds_dividers()
580 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_ss_dividers() local
582 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ss_dividers()
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/linux/drivers/infiniband/core/
H A Dcache.c382 struct ib_gid_table *table, int ix) in del_gid() argument
390 ix, table->data_vec[ix]->attr.gid.raw); in del_gid()
393 entry = table->data_vec[ix]; in del_gid()
399 table->data_vec[ix] = NULL; in del_gid()
552 int ix; in __ib_cache_gid_add() local
565 ix = find_gid(table, gid, attr, default_gid, mask, &empty); in __ib_cache_gid_add()
566 if (ix >= 0) in __ib_cache_gid_add()
606 int ix; in _ib_cache_gid_del() local
612 ix = find_gid(table, gid, attr, default_gid, mask, NULL); in _ib_cache_gid_del()
613 if (ix < 0) { in _ib_cache_gid_del()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/esw/
H A Dqos.c83 u32 ix; member
179 return vport->qos.sched_node->ix; in mlx5_esw_qos_vport_get_sched_elem_ix()
232 &node->ix); in esw_qos_node_create_sched_element()
248 node->ix); in esw_qos_node_destroy_sched_element()
287 node->ix, in esw_qos_sched_elem_config()
299 trace_mlx5_esw_node_qos_config(dev, node, node->ix, bw_share, max_rate); in esw_qos_sched_elem_config()
336 if (node->esw == esw && node->ix != esw->qos.root_tsar_ix && in esw_qos_calculate_min_rate_divider()
380 if (node->esw != esw || node->ix == esw->qos.root_tsar_ix) in esw_qos_normalize_min_rate()
476 parent ? parent->ix : vport_node->esw->qos.root_tsar_ix); in esw_qos_vport_create_sched_element()
507 vport_tc_node->parent->ix); in esw_qos_vport_tc_create_sched_element()
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/linux/drivers/s390/char/
H A Dcon3215.c176 int len, count, ix, lines; in raw3215_mk_write_req() local
201 ix = req->start; in raw3215_mk_write_req()
202 while (lines < RAW3215_MAX_NEWLINE && ix != raw->head) { in raw3215_mk_write_req()
203 if (raw->buffer[ix] == 0x15) in raw3215_mk_write_req()
205 ix = (ix + 1) & (RAW3215_BUFFER_SIZE - 1); in raw3215_mk_write_req()
207 len = ((ix - 1 - req->start) & (RAW3215_BUFFER_SIZE - 1)) + 1; in raw3215_mk_write_req()
214 req->delayable = (ix == raw->head) && (len < RAW3215_MIN_WRITE); in raw3215_mk_write_req()
216 ix = req->start; in raw3215_mk_write_req()
222 ccw->cda = virt_to_dma32(raw->buffer + ix); in raw3215_mk_write_req()
224 if (ix + count > RAW3215_BUFFER_SIZE) in raw3215_mk_write_req()
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