Searched refs:irq_handler_offset (Results 1 – 2 of 2) sorted by relevance
2553 u32 dma_qm_err_cfg, irq_handler_offset; in gaudi_init_pci_dma_qman() local2602 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ? in gaudi_init_pci_dma_qman()2615 lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_pci_dma_qman()2617 upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_pci_dma_qman()2642 u32 irq_handler_offset; in gaudi_init_dma_core() local2657 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ? in gaudi_init_dma_core()2662 lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_dma_core()2664 upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_dma_core()2732 u32 dma_qm_err_cfg, irq_handler_offset; in gaudi_init_hbm_dma_qman() local2773 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ? in gaudi_init_hbm_dma_qman()[all …]
5145 u32 glbl_prot = QMAN_MAKE_TRUSTED, irq_handler_offset; in gaudi2_init_qman_common() local5150 irq_handler_offset = gaudi2_get_dyn_sp_reg(hdev, queue_id_base); in gaudi2_init_qman_common()5151 WREG32(reg_base + QM_GLBL_ERR_ADDR_LO_OFFSET, lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_qman_common()5152 WREG32(reg_base + QM_GLBL_ERR_ADDR_HI_OFFSET, upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_qman_common()5195 u32 prot, irq_handler_offset; in gaudi2_init_dma_core() local5206 irq_handler_offset = le32_to_cpu(dyn_regs->gic_dma_core_irq_ctrl); in gaudi2_init_dma_core()5209 lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_dma_core()5212 upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_dma_core()11280 u32 irq_handler_offset = le32_to_cpu(dyn_regs->gic_host_ints_irq); in gaudi2_enable_events_from_fw() local11283 WREG32(irq_handler_offset, in gaudi2_enable_events_from_fw()