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Searched refs:interrupt_status_offsets (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c91 } interrupt_status_offsets[6] = { { variable
3107 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v8_0_crtc_irq()
3113 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v8_0_crtc_irq()
3124 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()
3228 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()
3229 mask = interrupt_status_offsets[hpd].hpd; in dce_v8_0_hpd_irq()
H A Ddce_v6_0.c96 } interrupt_status_offsets[6] = { { variable
3020 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v6_0_crtc_irq()
3026 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v6_0_crtc_irq()
3037 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()
3141 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()
3142 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()
H A Ddce_v10_0.c92 } interrupt_status_offsets[] = { { variable
3274 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq()
3279 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()
3291 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()
3320 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3321 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
H A Ddce_v11_0.c96 } interrupt_status_offsets[] = { { variable
3405 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v11_0_crtc_irq()
3411 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v11_0_crtc_irq()
3423 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v11_0_crtc_irq()
3452 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()
3453 mask = interrupt_status_offsets[hpd].hpd; in dce_v11_0_hpd_irq()