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Searched refs:interrupt_status_offsets (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c91 } interrupt_status_offsets[6] = { { variable
3101 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v8_0_crtc_irq()
3107 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v8_0_crtc_irq()
3118 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()
3222 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()
3223 mask = interrupt_status_offsets[hpd].hpd; in dce_v8_0_hpd_irq()
H A Ddce_v10_0.c92 } interrupt_status_offsets[] = { { variable
3268 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq()
3273 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()
3285 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()
3314 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3315 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
H A Ddce_v6_0.c103 } interrupt_status_offsets[6] = { { variable
3085 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v6_0_crtc_irq()
3091 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v6_0_crtc_irq()
3102 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()
3206 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()
3207 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()