Searched refs:int_params (Results 1 – 3 of 3) sorted by relevance
4290 struct dc_interrupt_params int_params = {0}; in register_hpd_handlers() local4292 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; in register_hpd_handlers()4293 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; in register_hpd_handlers()4325 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; in register_hpd_handlers()4326 int_params.irq_source = dc_link->irq_source_hpd; in register_hpd_handlers()4328 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || in register_hpd_handlers()4329 int_params.irq_source < DC_IRQ_SOURCE_HPD1 || in register_hpd_handlers()4330 int_params.irq_source > DC_IRQ_SOURCE_HPD6) { in register_hpd_handlers()4335 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, in register_hpd_handlers()4343 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; in register_hpd_handlers()[all …]
883 int n_msix = cdev->int_params.rdma_msix_cnt; in qed_rdma_get_min_cnq_msix()893 cdev->int_params.fp_initialized = cnt ? true : false; in qed_rdma_set_int()895 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) { in qed_rdma_set_int()898 cdev->int_params.out.int_mode); in qed_rdma_set_int()900 } else if (cdev->int_params.fp_msix_cnt) { in qed_rdma_set_int()901 limit = cdev->int_params.rdma_msix_cnt; in qed_rdma_set_int()914 if (!cdev->int_params.fp_initialized) { in qed_rdma_get_int()920 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { in qed_rdma_get_int()921 int msix_base = cdev->int_params.rdma_msix_base; in qed_rdma_get_int()923 info->msix_cnt = cdev->int_params.rdma_msix_cnt; in qed_rdma_get_int()[all …]
2207 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { in qed_fill_eth_dev_info()2228 if (cdev->int_params.fp_msix_cnt) { in qed_fill_eth_dev_info()2229 u8 irqs = cdev->int_params.fp_msix_cnt; in qed_fill_eth_dev_info()