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Searched refs:inst_idx (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c428 int inst_idx = vinst->inst; in vcn_v5_0_0_mc_resume_dpg_mode() local
432 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; in vcn_v5_0_0_mc_resume_dpg_mode()
438 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_0_mc_resume_dpg_mode()
439 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v5_0_0_mc_resume_dpg_mode()
440 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
441 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_0_mc_resume_dpg_mode()
442 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v5_0_0_mc_resume_dpg_mode()
443 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
444 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_0_mc_resume_dpg_mode()
445 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
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H A Dvcn_v4_0_5.c464 int inst_idx = vinst->inst; in vcn_v4_0_5_mc_resume_dpg_mode() local
468 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; in vcn_v4_0_5_mc_resume_dpg_mode()
474 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
475 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v4_0_5_mc_resume_dpg_mode()
476 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), in vcn_v4_0_5_mc_resume_dpg_mode()
478 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
479 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_5_mc_resume_dpg_mode()
480 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), in vcn_v4_0_5_mc_resume_dpg_mode()
482 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
483 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
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H A Dvcn_v3_0.c576 int inst_idx = vinst->inst; in vcn_v3_0_mc_resume_dpg_mode() local
577 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4); in vcn_v3_0_mc_resume_dpg_mode()
583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
584 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
585 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
586 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
587 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
588 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
589 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
590 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
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H A Dvcn_v4_0.c149 static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_fw_shared_init() argument
153 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v4_0_fw_shared_init()
169 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); in vcn_v4_0_fw_shared_init()
513 int inst_idx = vinst->inst; in vcn_v4_0_mc_resume_dpg_mode() local
516 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; in vcn_v4_0_mc_resume_dpg_mode()
522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
523 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v4_0_mc_resume_dpg_mode()
524 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
526 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_mc_resume_dpg_mode()
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H A Dvcn_v4_0_3.c99 int inst_idx, bool indirect);
167 static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_3_fw_shared_init() argument
171 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v4_0_3_fw_shared_init()
176 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); in vcn_v4_0_3_fw_shared_init()
314 int inst_idx = vinst->inst; in vcn_v4_0_3_hw_init_inst() local
316 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_hw_init_inst()
317 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v4_0_3_hw_init_inst()
321 adev->vcn.inst[inst_idx].aid_id); in vcn_v4_0_3_hw_init_inst()
472 int inst_idx = vinst->inst; in vcn_v4_0_3_mc_resume() local
476 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; in vcn_v4_0_3_mc_resume()
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H A Dvcn_v2_5.c648 int inst_idx = vinst->inst; in vcn_v2_5_mc_resume_dpg_mode() local
649 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4); in vcn_v2_5_mc_resume_dpg_mode()
655 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
657 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
658 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
660 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
661 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
664 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
666 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
668 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
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H A Djpeg_v5_3_0.c287 int inst_idx, uint8_t indirect) in jpeg_engine_5_0_0_dpg_clock_gating_mode() argument
301 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
305 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
307 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
311 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
324 static int jpeg_v5_3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v5_3_0_start_dpg_mode() argument
326 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v5_3_0_start_dpg_mode()
332 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v5_3_0_start_dpg_mode()
334 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); in jpeg_v5_3_0_start_dpg_mode()
337 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = in jpeg_v5_3_0_start_dpg_mode()
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H A Dvcn_v5_0_2.c80 static void vcn_v5_0_2_fw_shared_init(struct amdgpu_device *adev, int inst_idx) in vcn_v5_0_2_fw_shared_init() argument
84 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v5_0_2_fw_shared_init()
93 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); in vcn_v5_0_2_fw_shared_init()
385 int inst_idx = vinst->inst; in vcn_v5_0_2_mc_resume_dpg_mode() local
389 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; in vcn_v5_0_2_mc_resume_dpg_mode()
395 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_2_mc_resume_dpg_mode()
398 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
399 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_2_mc_resume_dpg_mode()
402 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
403 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_2_mc_resume_dpg_mode()
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H A Djpeg_v5_0_0.c304 int inst_idx, uint8_t indirect) in jpeg_engine_5_0_0_dpg_clock_gating_mode() argument
318 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
322 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
324 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
328 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
341 static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v5_0_0_start_dpg_mode() argument
343 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v5_0_0_start_dpg_mode()
349 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v5_0_0_start_dpg_mode()
351 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); in jpeg_v5_0_0_start_dpg_mode()
354 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = in jpeg_v5_0_0_start_dpg_mode()
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H A Djpeg_v4_0_5.c356 int inst_idx, uint8_t indirect) in jpeg_engine_4_0_5_dpg_clock_gating_mode() argument
367 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_CTRL_INTERNAL_OFFSET, data, indirect); in jpeg_engine_4_0_5_dpg_clock_gating_mode()
370 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_GATE_INTERNAL_OFFSET, in jpeg_engine_4_0_5_dpg_clock_gating_mode()
421 static void jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v4_0_5_start_dpg_mode() argument
423 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v4_0_5_start_dpg_mode()
427 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_start_dpg_mode()
430 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); in jpeg_v4_0_5_start_dpg_mode()
433 WREG32(SOC15_REG_OFFSET(JPEG, inst_idx, regUVD_IPX_DLDO_CONFIG), in jpeg_v4_0_5_start_dpg_mode()
435 SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_start_dpg_mode()
440 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_start_dpg_mode()
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H A Dvcn_v5_0_1.c137 static void vcn_v5_0_1_fw_shared_init(struct amdgpu_device *adev, int inst_idx) in vcn_v5_0_1_fw_shared_init() argument
141 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v5_0_1_fw_shared_init()
150 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); in vcn_v5_0_1_fw_shared_init()
488 int inst_idx = vinst->inst; in vcn_v5_0_1_mc_resume_dpg_mode() local
492 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; in vcn_v5_0_1_mc_resume_dpg_mode()
498 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_1_mc_resume_dpg_mode()
501 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
502 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_1_mc_resume_dpg_mode()
505 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
506 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_1_mc_resume_dpg_mode()
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H A Damdgpu_jpeg.c340 int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx, in amdgpu_jpeg_psp_update_sram() argument
345 .mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr, in amdgpu_jpeg_psp_update_sram()
346 .ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr - in amdgpu_jpeg_psp_update_sram()
347 (uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr), in amdgpu_jpeg_psp_update_sram()
H A Djpeg_v4_0_3.c493 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_disable_clock_gating() argument
498 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_disable_clock_gating()
518 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_enable_clock_gating() argument
523 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_enable_clock_gating()
H A Damdgpu_vcn.c1345 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, in amdgpu_vcn_psp_update_sram() argument
1350 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : in amdgpu_vcn_psp_update_sram()
1352 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, in amdgpu_vcn_psp_update_sram()
1353 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - in amdgpu_vcn_psp_update_sram()
1354 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), in amdgpu_vcn_psp_update_sram()
H A Dvcn_v2_0.c1294 int inst_idx = vinst->inst; in vcn_v2_0_pause_dpg_mode() local
1300 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_0_pause_dpg_mode()
1302 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_0_pause_dpg_mode()
1363 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_0_pause_dpg_mode()