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/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp9_if.c207 static bool vp9_is_sf_ref_fb(struct vdec_vp9_inst *inst, struct vdec_fb *fb) in vp9_is_sf_ref_fb() argument
210 struct vdec_vp9_vsi *vsi = inst->vsi; in vp9_is_sf_ref_fb()
220 *inst, void *addr) in vp9_rm_from_fb_use_list()
225 list_for_each_entry(node, &inst->fb_use_list, list) { in vp9_rm_from_fb_use_list()
229 &inst->available_fb_node_list); in vp9_rm_from_fb_use_list()
237 static void vp9_add_to_fb_free_list(struct vdec_vp9_inst *inst, in vp9_add_to_fb_free_list() argument
243 node = list_first_entry_or_null(&inst->available_fb_node_list, in vp9_add_to_fb_free_list()
248 list_move_tail(&node->list, &inst->fb_free_list); in vp9_add_to_fb_free_list()
251 mtk_vdec_debug(inst->ctx, "No free fb node"); in vp9_add_to_fb_free_list()
263 static void vp9_ref_cnt_fb(struct vdec_vp9_inst *inst, int *idx, in vp9_ref_cnt_fb() argument
[all …]
H A Dvdec_vp8_if.c165 static void get_hw_reg_base(struct vdec_vp8_inst *inst) in get_hw_reg_base() argument
167 void __iomem **reg_base = inst->ctx->dev->reg_base; in get_hw_reg_base()
169 inst->reg_base.top = mtk_vcodec_get_reg_addr(reg_base, VDEC_TOP); in get_hw_reg_base()
170 inst->reg_base.cm = mtk_vcodec_get_reg_addr(reg_base, VDEC_CM); in get_hw_reg_base()
171 inst->reg_base.hwd = mtk_vcodec_get_reg_addr(reg_base, VDEC_HWD); in get_hw_reg_base()
172 inst->reg_base.misc = mtk_vcodec_get_reg_addr(reg_base, VDEC_MISC); in get_hw_reg_base()
173 inst->reg_base.ld = mtk_vcodec_get_reg_addr(reg_base, VDEC_LD); in get_hw_reg_base()
174 inst->reg_base.hwb = mtk_vcodec_get_reg_addr(reg_base, VDEC_HWB); in get_hw_reg_base()
177 static void write_hw_segmentation_data(struct vdec_vp8_inst *inst) in write_hw_segmentation_data() argument
182 void __iomem *cm = inst->reg_base.cm; in write_hw_segmentation_data()
[all …]
H A Dvdec_h264_if.c139 static int allocate_prediction_buf(struct vdec_h264_inst *inst) in allocate_prediction_buf() argument
143 inst->pred_buf.size = BUF_PREDICTION_SZ; in allocate_prediction_buf()
144 err = mtk_vcodec_mem_alloc(inst->ctx, &inst->pred_buf); in allocate_prediction_buf()
146 mtk_vdec_err(inst->ctx, "failed to allocate ppl buf"); in allocate_prediction_buf()
150 inst->vsi->pred_buf_dma = inst->pred_buf.dma_addr; in allocate_prediction_buf()
154 static void free_prediction_buf(struct vdec_h264_inst *inst) in free_prediction_buf() argument
158 inst->vsi->pred_buf_dma = 0; in free_prediction_buf()
159 mem = &inst->pred_buf; in free_prediction_buf()
161 mtk_vcodec_mem_free(inst->ctx, mem); in free_prediction_buf()
164 static int alloc_mv_buf(struct vdec_h264_inst *inst, struct vdec_pic_info *pic) in alloc_mv_buf() argument
[all …]
/linux/drivers/media/platform/amphion/
H A Dvpu_cmds.c81 static struct vpu_cmd_t *vpu_alloc_cmd(struct vpu_inst *inst, u32 id, void *data) in vpu_alloc_cmd() argument
98 ret = vpu_iface_pack_cmd(inst->core, cmd->pkt, inst->id, id, data); in vpu_alloc_cmd()
100 dev_err(inst->dev, "iface pack cmd %s fail\n", vpu_id_name(id)); in vpu_alloc_cmd()
125 static int vpu_session_process_cmd(struct vpu_inst *inst, struct vpu_cmd_t *cmd) in vpu_session_process_cmd() argument
129 dev_dbg(inst->dev, "[%d]send cmd %s\n", inst->id, vpu_id_name(cmd->id)); in vpu_session_process_cmd()
130 vpu_iface_pre_send_cmd(inst); in vpu_session_process_cmd()
131 ret = vpu_cmd_send(inst->core, cmd->pkt); in vpu_session_process_cmd()
133 vpu_iface_post_send_cmd(inst); in vpu_session_process_cmd()
134 vpu_inst_record_flow(inst, cmd->id); in vpu_session_process_cmd()
136 dev_err(inst->dev, "[%d] iface send cmd %s fail\n", inst->id, vpu_id_name(cmd->id)); in vpu_session_process_cmd()
[all …]
H A Dvpu_msgs.c25 void (*done)(struct vpu_inst *inst, struct vpu_rpc_event *pkt);
29 static void vpu_session_handle_start_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt) in vpu_session_handle_start_done() argument
31 vpu_trace(inst->dev, "[%d]\n", inst->id); in vpu_session_handle_start_done()
34 static void vpu_session_handle_mem_request(struct vpu_inst *inst, struct vpu_rpc_event *pkt) in vpu_session_handle_mem_request() argument
38 vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&req_data); in vpu_session_handle_mem_request()
39 vpu_trace(inst->dev, "[%d] %d:%d %d:%d %d:%d\n", in vpu_session_handle_mem_request()
40 inst->id, in vpu_session_handle_mem_request()
47 vpu_inst_lock(inst); in vpu_session_handle_mem_request()
48 call_void_vop(inst, mem_request, in vpu_session_handle_mem_request()
55 vpu_inst_unlock(inst); in vpu_session_handle_mem_request()
[all …]
H A Dvpu_rpc.h70 struct vpu_inst *inst, struct vb2_buffer *vb);
115 struct vpu_iface_ops *vpu_inst_get_iface(struct vpu_inst *inst);
128 static inline bool vpu_iface_check_format(struct vpu_inst *inst, u32 pixelfmt) in vpu_iface_check_format() argument
130 struct vpu_iface_ops *ops = vpu_inst_get_iface(inst); in vpu_iface_check_format()
133 return ops->check_fmt(inst->type, pixelfmt); in vpu_iface_check_format()
248 static inline int vpu_iface_config_stream(struct vpu_inst *inst) in vpu_iface_config_stream() argument
250 struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); in vpu_iface_config_stream()
252 if (!ops || inst->id < 0) in vpu_iface_config_stream()
255 ops->set_stream_cfg(inst->core->iface, inst->id); in vpu_iface_config_stream()
311 static inline int vpu_iface_input_frame(struct vpu_inst *inst, in vpu_iface_input_frame() argument
[all …]
/linux/drivers/media/platform/mediatek/vcodec/encoder/venc/
H A Dvenc_vp8_if.c134 static inline u32 vp8_enc_read_reg(struct venc_vp8_inst *inst, u32 addr) in vp8_enc_read_reg() argument
136 return readl(inst->hw_base + addr); in vp8_enc_read_reg()
139 static void vp8_enc_free_work_buf(struct venc_vp8_inst *inst) in vp8_enc_free_work_buf() argument
145 if (inst->work_bufs[i].size == 0) in vp8_enc_free_work_buf()
147 mtk_vcodec_mem_free(inst->ctx, &inst->work_bufs[i]); in vp8_enc_free_work_buf()
151 static int vp8_enc_alloc_work_buf(struct venc_vp8_inst *inst) in vp8_enc_alloc_work_buf() argument
155 struct venc_vp8_vpu_buf *wb = inst->vsi->work_bufs; in vp8_enc_alloc_work_buf()
170 inst->work_bufs[i].size = wb[i].size; in vp8_enc_alloc_work_buf()
171 ret = mtk_vcodec_mem_alloc(inst->ctx, &inst->work_bufs[i]); in vp8_enc_alloc_work_buf()
173 mtk_venc_err(inst->ctx, "cannot alloc work_bufs[%d]", i); in vp8_enc_alloc_work_buf()
[all …]
/linux/drivers/media/platform/qcom/iris/
H A Diris_hfi_gen2_command.c91 static u32 iris_hfi_gen2_get_port(struct iris_inst *inst, u32 plane) in iris_hfi_gen2_get_port() argument
93 if (inst->domain == DECODER) { in iris_hfi_gen2_get_port()
114 static u32 iris_hfi_gen2_get_port_from_buf_type(struct iris_inst *inst, in iris_hfi_gen2_get_port_from_buf_type() argument
117 if (inst->domain == DECODER) { in iris_hfi_gen2_get_port_from_buf_type()
151 static int iris_hfi_gen2_session_set_property(struct iris_inst *inst, u32 packet_type, u32 flag, in iris_hfi_gen2_session_set_property() argument
155 struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst); in iris_hfi_gen2_session_set_property()
157 iris_hfi_gen2_packet_session_property(inst, in iris_hfi_gen2_session_set_property()
165 return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet, in iris_hfi_gen2_session_set_property()
169 static int iris_hfi_gen2_set_raw_resolution(struct iris_inst *inst, u32 plane) in iris_hfi_gen2_set_raw_resolution() argument
171 u32 resolution = inst->fmt_src->fmt.pix_mp.width << 16 | in iris_hfi_gen2_set_raw_resolution()
[all …]
/linux/arch/powerpc/include/asm/
H A Ddisassemble.h14 static inline unsigned int get_op(u32 inst) in get_op() argument
16 return inst >> 26; in get_op()
19 static inline unsigned int get_xop(u32 inst) in get_xop() argument
21 return (inst >> 1) & 0x3ff; in get_xop()
24 static inline unsigned int get_sprn(u32 inst) in get_sprn() argument
26 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_sprn()
29 static inline unsigned int get_dcrn(u32 inst) in get_dcrn() argument
31 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_dcrn()
34 static inline unsigned int get_tmrn(u32 inst) in get_tmrn() argument
36 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_tmrn()
[all …]
/linux/net/netfilter/
H A Dnfnetlink_log.c109 struct nfulnl_instance *inst; in __instance_lookup() local
112 hlist_for_each_entry_rcu(inst, head, hlist) { in __instance_lookup()
113 if (inst->group_num == group_num) in __instance_lookup()
114 return inst; in __instance_lookup()
120 instance_get(struct nfulnl_instance *inst) in instance_get() argument
122 refcount_inc(&inst->use); in instance_get()
128 struct nfulnl_instance *inst; in instance_lookup_get_rcu() local
130 inst = __instance_lookup(log, group_num); in instance_lookup_get_rcu()
131 if (inst && !refcount_inc_not_zero(&inst->use)) in instance_lookup_get_rcu()
132 inst = NULL; in instance_lookup_get_rcu()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv25.c37 &chan->inst); in nv25_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv25_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); in nv25_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000); in nv25_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000); in nv25_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x049c, 0x00000101); in nv25_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x04b0, 0x00000111); in nv25_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x04c8, 0x00000080); in nv25_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x04cc, 0xffff0000); in nv25_gr_chan_new()
[all …]
H A Dnv35.c37 &chan->inst); in nv35_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv35_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x00000101); in nv35_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv35_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv35_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv35_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv35_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv35_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv35_gr_chan_new()
[all …]
H A Dnv34.c37 &chan->inst); in nv34_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv34_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv34_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x01000101); in nv34_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv34_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv34_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv34_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv34_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv34_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv34_gr_chan_new()
[all …]
H A Dnv2a.c37 &chan->inst); in nv2a_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv2a_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); in nv2a_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x033c, 0xffff0000); in nv2a_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); in nv2a_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); in nv2a_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x047c, 0x00000101); in nv2a_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0490, 0x00000111); in nv2a_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x04a8, 0x44400000); in nv2a_gr_chan_new()
50 nvkm_wo32(chan->inst, i, 0x00030303); in nv2a_gr_chan_new()
[all …]
H A Dnv30.c38 &chan->inst); in nv30_gr_chan_new()
42 nvkm_kmap(chan->inst); in nv30_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv30_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0410, 0x00000101); in nv30_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000111); in nv30_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0428, 0x00000060); in nv30_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0x00000080); in nv30_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0xffff0000); in nv30_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x044c, 0x00000001); in nv30_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0460, 0x44400000); in nv30_gr_chan_new()
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-xsphy.c122 struct xsphy_instance *inst) in u2_phy_slew_rate_calibrate() argument
124 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
130 if (inst->eye_src) in u2_phy_slew_rate_calibrate()
169 inst->index, fm_out, calib_val, in u2_phy_slew_rate_calibrate()
180 struct xsphy_instance *inst) in u2_phy_instance_init() argument
182 void __iomem *pbase = inst->port_base; in u2_phy_instance_init()
191 struct xsphy_instance *inst) in u2_phy_instance_power_on() argument
193 void __iomem *pbase = inst->port_base; in u2_phy_instance_power_on()
194 u32 index = inst->index; in u2_phy_instance_power_on()
206 struct xsphy_instance *inst) in u2_phy_instance_power_off() argument
[all …]
/linux/arch/arm64/kernel/
H A Dkuser32.S24 .inst 0xe92d00f0 // push {r4, r5, r6, r7}
25 .inst 0xe1c040d0 // ldrd r4, r5, [r0]
26 .inst 0xe1c160d0 // ldrd r6, r7, [r1]
27 .inst 0xe1b20f9f // 1: ldrexd r0, r1, [r2]
28 .inst 0xe0303004 // eors r3, r0, r4
29 .inst 0x00313005 // eoreqs r3, r1, r5
30 .inst 0x01a23e96 // stlexdeq r3, r6, [r2]
31 .inst 0x03330001 // teqeq r3, #1
32 .inst 0x0afffff9 // beq 1b
33 .inst 0xf57ff05b // dmb ish
[all …]
/linux/drivers/media/platform/qcom/venus/
H A Dhelpers.h14 bool venus_helper_check_codec(struct venus_inst *inst, u32 v4l2_pixfmt);
15 struct vb2_v4l2_buffer *venus_helper_find_buf(struct venus_inst *inst,
17 void venus_helper_change_dpb_owner(struct venus_inst *inst,
20 void venus_helper_buffers_done(struct venus_inst *inst, unsigned int type,
26 int venus_helper_vb2_start_streaming(struct venus_inst *inst);
27 void venus_helper_vb2_queue_error(struct venus_inst *inst);
30 int venus_helper_get_bufreq(struct venus_inst *inst, u32 type,
34 int venus_helper_set_input_resolution(struct venus_inst *inst,
36 int venus_helper_set_output_resolution(struct venus_inst *inst,
39 int venus_helper_set_work_mode(struct venus_inst *inst);
[all …]
H A Dhfi_parser.h8 u32 hfi_parser(struct venus_core *core, struct venus_inst *inst,
15 static inline u32 get_cap(struct venus_inst *inst, u32 type, u32 which) in get_cap() argument
17 struct venus_core *core = inst->core; in get_cap()
22 caps = venus_caps_by_codec(core, inst->hfi_codec, inst->session_type); in get_cap()
50 static inline u32 cap_min(struct venus_inst *inst, u32 type) in cap_min() argument
52 return get_cap(inst, type, WHICH_CAP_MIN); in cap_min()
55 static inline u32 cap_max(struct venus_inst *inst, u32 type) in cap_max() argument
57 return get_cap(inst, type, WHICH_CAP_MAX); in cap_max()
60 static inline u32 cap_step(struct venus_inst *inst, u32 type) in cap_step() argument
62 return get_cap(inst, type, WHICH_CAP_STEP); in cap_step()
[all …]
/linux/arch/powerpc/kernel/
H A Dkvm.c71 static void __init kvm_patch_ins(u32 *inst, u32 new_inst) in kvm_patch_ins() argument
73 *inst = new_inst; in kvm_patch_ins()
74 flush_icache_range((ulong)inst, (ulong)inst + 4); in kvm_patch_ins()
77 static void __init kvm_patch_ins_ll(u32 *inst, long addr, u32 rt) in kvm_patch_ins_ll() argument
80 kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc)); in kvm_patch_ins_ll()
82 kvm_patch_ins(inst, KVM_INST_LWZ | rt | (addr & 0x0000fffc)); in kvm_patch_ins_ll()
86 static void __init kvm_patch_ins_ld(u32 *inst, long addr, u32 rt) in kvm_patch_ins_ld() argument
89 kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc)); in kvm_patch_ins_ld()
91 kvm_patch_ins(inst, KVM_INST_LWZ | rt | ((addr + 4) & 0x0000fffc)); in kvm_patch_ins_ld()
95 static void __init kvm_patch_ins_lwz(u32 *inst, long addr, u32 rt) in kvm_patch_ins_lwz() argument
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h28 #define GET_INST(ip, inst) \ argument
30 adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst)
36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) argument
37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \ argument
38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ argument
42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ argument
47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
66 #define RREG32_SOC15(ip, inst, reg) \ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.h34 #define MCIF_WB_COMMON_REG_LIST_DCN3_0(inst) \ argument
35 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
36 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
37 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
38 SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
39 SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
40 SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
41 SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
42 SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
43 SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
[all …]
/linux/arch/arm/mach-omap2/
H A Dcm33xx.c46 static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) in am33xx_cm_read_reg() argument
48 return readl_relaxed(cm_base.va + inst + idx); in am33xx_cm_read_reg()
52 static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) in am33xx_cm_write_reg() argument
54 writel_relaxed(val, cm_base.va + inst + idx); in am33xx_cm_write_reg()
58 static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) in am33xx_cm_rmw_reg_bits() argument
62 v = am33xx_cm_read_reg(inst, idx); in am33xx_cm_rmw_reg_bits()
65 am33xx_cm_write_reg(v, inst, idx); in am33xx_cm_rmw_reg_bits()
70 static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask) in am33xx_cm_read_reg_bits() argument
74 v = am33xx_cm_read_reg(inst, idx); in am33xx_cm_read_reg_bits()
89 static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs) in _clkctrl_idlest() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
H A Ddcn32_mmhubbub.h32 #define MCIF_WB_COMMON_REG_LIST_DCN32(inst) \ argument
33 SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
34 SRI2(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
35 SRI2(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
36 SRI2(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
37 SRI2(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
38 SRI2(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
39 SRI2(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
40 SRI2(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
41 SRI2(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
H A Ddcn20_mpc.h33 #define MPC_REG_LIST_DCN2_0(inst)\ argument
34 MPC_COMMON_REG_LIST_DCN1_0(inst),\
35 SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
37 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
38 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
39 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
40 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
41 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
42 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
[all …]

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