Searched refs:input_reg (Results 1 – 6 of 6) sorted by relevance
65 int mux_reg, conf_reg, input_reg, mux_val, conf_val, input_val; in pinctrl_scmi_imx_dt_node_to_map() local109 input_reg = be32_to_cpu(*list++); in pinctrl_scmi_imx_dt_node_to_map()125 if (!input_reg) { in pinctrl_scmi_imx_dt_node_to_map()129 (input_reg - daisy_off) / 4); in pinctrl_scmi_imx_dt_node_to_map()
220 val = readl(ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()223 writel(val, ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()224 } else if (pin_mmio->input_reg) { in imx_pmx_set_one_pin_mmio()231 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()234 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()237 pin_mmio->input_reg, pin_mmio->input_val); in imx_pmx_set_one_pin_mmio()490 pin_mmio->input_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
31 u16 input_reg; member
17 <mux_conf_reg input_reg mux_mode input_val> are specified
26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
901 bool input_reg = !iqs5xx->input; in fw_file_store() local925 if (input_reg) { in fw_file_store()