Searched refs:input_clock (Results 1 – 10 of 10) sorted by relevance
168 if (chip->input_clock != ECHO_CLOCK_INTERNAL) { in set_sample_rate()214 chip->input_clock = clock_source; in set_input_clock()216 chip->comm_page->input_clock = cpu_to_le16(clock); in set_input_clock()
146 if (chip->input_clock == ECHO_CLOCK_ESYNC) in set_sample_rate()162 chip->input_clock = clock; in set_input_clock()
160 chip->input_clock = clock; in set_input_clock()168 chip->input_clock = clock; in set_input_clock()
136 if (chip->input_clock == ECHO_CLOCK_SPDIF) in set_sample_rate()163 chip->input_clock = clock; in set_input_clock()
103 return set_input_clock(chip, chip->input_clock); in set_input_auto_mute()
680 __le16 input_clock; /* Chg. Input clock state 0xb68 2 */ member
377 u8 input_clock; /* Currently selected sample clock member
754 if (set_input_clock(chip, chip->input_clock) < 0) in restore_dsp_rettings()1014 chip->input_clock = ECHO_CLOCK_INTERNAL; in init_line_levels()
175 u32 input_clock = clk_get_rate(dev->clk); in i2c_davinci_calc_clk_dividers() local204 psc = (input_clock / 12000000) - 1; in i2c_davinci_calc_clk_dividers()205 if ((input_clock / (psc + 1)) > 12000000) in i2c_davinci_calc_clk_dividers()212 clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)); in i2c_davinci_calc_clk_dividers()214 if (input_clock / (psc + 1) / clk > dev->bus_freq * 1000) in i2c_davinci_calc_clk_dividers()245 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk); in i2c_davinci_calc_clk_dividers()
1108 static struct clk __init *input_clock(const char *name, struct clk *clk) in input_clock() function1132 return input_clock(name, clk); in input_clock_by_name()1143 return input_clock(name, clk); in input_clock_by_index()