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Searched refs:input_clks (Results 1 – 1 of 1) sorted by relevance

/linux/drivers/phy/cadence/
H A Dphy-cadence-sierra.c405 struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; member
560 clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); in cdns_sierra_phy_init()
561 clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); in cdns_sierra_phy_init()
1166 sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; in cdns_sierra_phy_get_clocks()
1174 sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; in cdns_sierra_phy_get_clocks()
1190 sp->input_clks[PHY_CLK] = clk; in cdns_sierra_phy_clk()
1192 ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); in cdns_sierra_phy_clk()
1224 clk_disable_unprepare(sp->input_clks[PHY_CLK]); in cdns_sierra_phy_disable_clocks()
1266 clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000); in cdns_sierra_phy_configure_multilink()
1267 clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); in cdns_sierra_phy_configure_multilink()