Home
last modified time | relevance | path

Searched refs:initial_offset (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c205 pps_payload->initial_offset = in drm_dsc_pps_payload_pack()
206 cpu_to_be16(dsc_cfg->initial_offset); in drm_dsc_pps_payload_pack()
334 u16 initial_offset; member
1278 vdsc_cfg->initial_offset = rc_params->initial_offset; in drm_dsc_setup_rc_params()
1398 vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()
1427 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()
1461 return 8 * dsc->rc_model_size / (dsc->rc_model_size - dsc->initial_offset); in drm_dsc_initial_scale_value()
1499 cfg->initial_offset, cfg->final_offset, cfg->slice_bpg_offset); in drm_dsc_dump_config_main_params()
/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Drc_calc_dpi.c52 to->initial_offset = from->initial_offset; in copy_pps_fields()
77 dsc_cfg->initial_offset = rc->initial_fullness_offset; in copy_rc_to_cfg()
/linux/drivers/media/test-drivers/vidtv/
H A Dvidtv_mux.c158 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_push_si() local
214 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_push_si()
285 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_packetize_access_units() local
318 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_packetize_access_units()
356 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_pad_with_nulls() local
370 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_pad_with_nulls()
/linux/include/drm/display/
H A Ddrm_dsc.h169 u16 initial_offset; member
442 __be16 initial_offset; member
/linux/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c122 vdsc_cfg->initial_offset = 2048; in calculate_rc_params()
124 vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); in calculate_rc_params()
126 vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); in calculate_rc_params()
128 vdsc_cfg->initial_offset = 6144; in calculate_rc_params()
351 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()
509 DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset); in intel_dsc_pps_configure()
930 vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
H A Dintel_vdsc_regs.h153 #define DSC_PPS8_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \ argument
154 initial_offset)
/linux/drivers/nvdimm/
H A Dbtt_devs.c280 nd_btt->initial_offset = 0; in nd_btt_version()
295 nd_btt->initial_offset = SZ_4K; in nd_btt_version()
H A Dbtt.c36 return offset + nd_btt->initial_offset; in adjust_initial_offset()
1672 rawsize = size - nd_btt->initial_offset; in nvdimm_namespace_attach_btt()
1676 ARENA_MIN_SIZE + nd_btt->initial_offset); in nvdimm_namespace_attach_btt()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dsc.c107 data = dsc->initial_offset << 16; in dpu_hw_dsc_config()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c315 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); in dsc_log_pps()
555 reg_vals->pps.initial_offset = 6144; in dsc_init_reg_values()
678 INITIAL_OFFSET, reg_vals->pps.initial_offset, in dsc_write_to_registers()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c318 INITIAL_OFFSET, reg_vals->pps.initial_offset, in dsc_write_to_registers()