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Searched refs:imx_clk_gate (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/clk/imx/
H A Dclk-imx25.c108 clk[cko] = imx_clk_gate("cko", "cko_div", ccm(CCM_MCR), 30); in __mx25_clocks_init()
125 clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0); in __mx25_clocks_init()
126 clk[epit_ipg_per] = imx_clk_gate("epit_ipg_per", "per1", ccm(CCM_CGCR0), 1); in __mx25_clocks_init()
127 clk[esai_ipg_per] = imx_clk_gate("esai_ipg_per", "per2", ccm(CCM_CGCR0), 2); in __mx25_clocks_init()
128 clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3); in __mx25_clocks_init()
129 clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4); in __mx25_clocks_init()
130 clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5); in __mx25_clocks_init()
131 clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6); in __mx25_clocks_init()
132 clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7); in __mx25_clocks_init()
133 clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8); in __mx25_clocks_init()
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H A Dclk-imx1.c43 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); in mx1_clocks_init_dt()
47 clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); in mx1_clocks_init_dt()
49 clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in mx1_clocks_init_dt()
58 clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6); in mx1_clocks_init_dt()
59 clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5); in mx1_clocks_init_dt()
60 clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4); in mx1_clocks_init_dt()
61 clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3); in mx1_clocks_init_dt()
62 clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2); in mx1_clocks_init_dt()
63 clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); in mx1_clocks_init_dt()
64 clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); in mx1_clocks_init_dt()
H A Dclk.h133 #define imx_clk_gate(name, parent, reg, shift) \ macro