Searched refs:idx_value (Results 1 – 4 of 4) sorted by relevance
637 u32 idx_value; in r300_packet0_check() local641 idx_value = radeon_get_ib_value(p, idx); in r300_packet0_check()673 track->cb[i].offset = idx_value; in r300_packet0_check()675 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()686 track->zb.offset = idx_value; in r300_packet0_check()688 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()716 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ in r300_packet0_check()717 ((idx_value & ~31) + (u32)reloc->gpu_offset); in r300_packet0_check()726 tmp = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()736 track->vap_vf_cntl = idx_value; in r300_packet0_check()[all …]
1339 u32 idx_value; in r100_packet3_load_vbpntr() local1359 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()1362 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()1374 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()1385 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()1388 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()1591 u32 idx_value; in r100_packet0_check() local1596 idx_value = radeon_get_ib_value(p, idx); in r100_packet0_check()1625 track->zb.offset = idx_value; in r100_packet0_check()1627 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()[all …]
1641 u32 idx_value; in r600_packet3_check() local1646 idx_value = radeon_get_ib_value(p, idx); in r600_packet3_check()1679 (idx_value & 0xfffffff0) + in r600_packet3_check()1720 idx_value + in r600_packet3_check()1762 if (idx_value & 0x10) { in r600_packet3_check()1777 } else if (idx_value & 0x100) { in r600_packet3_check()1914 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; in r600_packet3_check()1930 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; in r600_packet3_check()1950 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; in r600_packet3_check()2030 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; in r600_packet3_check()[all …]
1783 u32 idx_value; in evergreen_packet3_check() local1788 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()1821 (idx_value & 0xfffffff0) + in evergreen_packet3_check()1867 idx_value + in evergreen_packet3_check()1902 idx_value + in evergreen_packet3_check()2013 if (idx_value != 1) { in evergreen_packet3_check()2046 if (idx_value + size > track->indirect_draw_buffer_size) { in evergreen_packet3_check()2048 idx_value, size, track->indirect_draw_buffer_size); in evergreen_packet3_check()2080 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()2093 if (idx_value & 0x10) { in evergreen_packet3_check()[all …]