| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.c | 218 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn301_smu_set_display_idle_optimization() argument
222 DC_LOG_DEBUG("%s(%x)\n", __func__, idle_info); in dcn301_smu_set_display_idle_optimization()
227 idle_info); in dcn301_smu_set_display_idle_optimization()
232 union display_idle_optimization_u idle_info = { 0 }; in dcn301_smu_enable_phy_refclk_pwrdwn() local
235 idle_info.idle_info.df_request_disabled = 1; in dcn301_smu_enable_phy_refclk_pwrdwn()
236 idle_info.idle_info.phy_ref_clk_off = 1; in dcn301_smu_enable_phy_refclk_pwrdwn()
244 idle_info.data); in dcn301_smu_enable_phy_refclk_pwrdwn()
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| H A D | vg_clk_mgr.c | 121 union display_idle_optimization_u idle_info = { 0 }; in vg_update_clocks() local
123 idle_info.idle_info.df_request_disabled = 1; in vg_update_clocks()
124 idle_info.idle_info.phy_ref_clk_off = 1; in vg_update_clocks()
126 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in vg_update_clocks()
134 union display_idle_optimization_u idle_info = { 0 }; in vg_update_clocks() local
136 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in vg_update_clocks()
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| H A D | dcn301_smu.h | 145 struct display_idle_optimization idle_info; member
156 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.c | 228 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn316_smu_set_display_idle_optimization() argument
240 idle_info); in dcn316_smu_set_display_idle_optimization()
245 union display_idle_optimization_u idle_info = { 0 }; in dcn316_smu_enable_phy_refclk_pwrdwn() local
251 idle_info.idle_info.df_request_disabled = 1; in dcn316_smu_enable_phy_refclk_pwrdwn()
252 idle_info.idle_info.phy_ref_clk_off = 1; in dcn316_smu_enable_phy_refclk_pwrdwn()
258 idle_info.data); in dcn316_smu_enable_phy_refclk_pwrdwn()
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| H A D | dcn316_clk_mgr.c | 166 union display_idle_optimization_u idle_info = { 0 }; in dcn316_update_clocks() local
167 idle_info.idle_info.df_request_disabled = 1; in dcn316_update_clocks()
168 idle_info.idle_info.phy_ref_clk_off = 1; in dcn316_update_clocks()
169 idle_info.idle_info.s0i2_rdy = 1; in dcn316_update_clocks()
170 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn316_update_clocks()
183 union display_idle_optimization_u idle_info = { 0 }; in dcn316_update_clocks() local
184 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn316_update_clocks()
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| H A D | dcn316_smu.h | 118 struct display_idle_optimization idle_info; member
127 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 259 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn314_smu_set_display_idle_optimization() argument
271 idle_info); in dcn314_smu_set_display_idle_optimization()
276 union display_idle_optimization_u idle_info = { 0 }; in dcn314_smu_enable_phy_refclk_pwrdwn() local
282 idle_info.idle_info.df_request_disabled = 1; in dcn314_smu_enable_phy_refclk_pwrdwn()
283 idle_info.idle_info.phy_ref_clk_off = 1; in dcn314_smu_enable_phy_refclk_pwrdwn()
289 idle_info.data); in dcn314_smu_enable_phy_refclk_pwrdwn()
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| H A D | dcn314_smu.h | 89 struct display_idle_optimization idle_info; member
99 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.c | 240 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn31_smu_set_display_idle_optimization() argument
252 idle_info); in dcn31_smu_set_display_idle_optimization()
257 union display_idle_optimization_u idle_info = { 0 }; in dcn31_smu_enable_phy_refclk_pwrdwn() local
263 idle_info.idle_info.df_request_disabled = 1; in dcn31_smu_enable_phy_refclk_pwrdwn()
264 idle_info.idle_info.phy_ref_clk_off = 1; in dcn31_smu_enable_phy_refclk_pwrdwn()
270 idle_info.data); in dcn31_smu_enable_phy_refclk_pwrdwn()
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| H A D | dcn31_smu.h | 250 struct display_idle_optimization idle_info; member
260 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.c | 254 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn315_smu_set_display_idle_optimization() argument
266 idle_info); in dcn315_smu_set_display_idle_optimization()
271 union display_idle_optimization_u idle_info = { 0 }; in dcn315_smu_enable_phy_refclk_pwrdwn() local
277 idle_info.idle_info.df_request_disabled = 1; in dcn315_smu_enable_phy_refclk_pwrdwn()
278 idle_info.idle_info.phy_ref_clk_off = 1; in dcn315_smu_enable_phy_refclk_pwrdwn()
284 idle_info.data); in dcn315_smu_enable_phy_refclk_pwrdwn()
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| H A D | dcn315_clk_mgr.c | 157 union display_idle_optimization_u idle_info = { 0 }; in dcn315_update_clocks() local
158 idle_info.idle_info.df_request_disabled = 1; in dcn315_update_clocks()
159 idle_info.idle_info.phy_ref_clk_off = 1; in dcn315_update_clocks()
160 idle_info.idle_info.s0i2_rdy = 1; in dcn315_update_clocks()
161 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn315_update_clocks()
173 union display_idle_optimization_u idle_info = { 0 }; in dcn315_update_clocks() local
174 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn315_update_clocks()
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| H A D | dcn315_smu.h | 110 struct display_idle_optimization idle_info; member
119 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_smu.c | 278 void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn35_smu_set_display_idle_optimization() argument
290 idle_info); in dcn35_smu_set_display_idle_optimization()
291 smu_print("%s: VBIOSSMC_MSG_SetDisplayIdleOptimizations idle_info = %x\n", __func__, idle_info); in dcn35_smu_set_display_idle_optimization()
296 union display_idle_optimization_u idle_info = { 0 }; in dcn35_smu_enable_phy_refclk_pwrdwn() local
302 idle_info.idle_info.df_request_disabled = 1; in dcn35_smu_enable_phy_refclk_pwrdwn()
303 idle_info.idle_info.phy_ref_clk_off = 1; in dcn35_smu_enable_phy_refclk_pwrdwn()
309 idle_info.data); in dcn35_smu_enable_phy_refclk_pwrdwn()
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| H A D | dcn35_smu.h | 175 struct display_idle_optimization idle_info; member
185 void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| H A D | dcn35_clk_mgr.c | 367 union display_idle_optimization_u idle_info = { 0 }; in dcn35_update_clocks() local
369 dcn35_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn35_update_clocks()
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