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Searched refs:hybrid_var (Results 1 – 4 of 4) sorted by relevance

/linux/arch/x86/events/intel/
H A Dds.c324 val = hybrid_var(event->pmu, pebs_data_source)[dse]; in __grt_latency_data()
368 val = hybrid_var(event->pmu, pebs_data_source)[status & PERF_PEBS_DATA_SOURCE_MASK]; in lnc_latency_data()
424 val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse]; in load_latency_data()
474 val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse]; in store_latency_data()
H A Dcore.c3714 return &hybrid_var(cpuc->pmu, unconstrained); in x86_get_event_constraints()
7175 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); in intel_pmu_init_glc()
7176 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); in intel_pmu_init_glc()
7194 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); in intel_pmu_init_grt()
7195 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); in intel_pmu_init_grt()
7196 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init_grt()
/linux/arch/x86/events/
H A Dcore.c398 val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result]; in set_ext_hw_attr()
406 attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result]; in set_ext_hw_attr()
H A Dperf_event.h787 #define hybrid_var(_pmu, _var) \ macro