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Searched refs:hwseq (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c88 static bool gpu_addr_to_uma(struct dce_hwseq *hwseq, in gpu_addr_to_uma() argument
93 if (hwseq->fb_base.quad_part <= addr->quad_part && in gpu_addr_to_uma()
94 addr->quad_part < hwseq->fb_top.quad_part) { in gpu_addr_to_uma()
95 addr->quad_part -= hwseq->fb_base.quad_part; in gpu_addr_to_uma()
96 addr->quad_part += hwseq->fb_offset.quad_part; in gpu_addr_to_uma()
98 } else if (hwseq->fb_offset.quad_part <= addr->quad_part && in gpu_addr_to_uma()
99 addr->quad_part <= hwseq->uma_top.quad_part) { in gpu_addr_to_uma()
110 static void plane_address_in_gpu_space_to_uma(struct dce_hwseq *hwseq, in plane_address_in_gpu_space_to_uma() argument
115 gpu_addr_to_uma(hwseq, &addr->grph.addr); in plane_address_in_gpu_space_to_uma()
116 gpu_addr_to_uma(hwseq, &addr->grph.meta_addr); in plane_address_in_gpu_space_to_uma()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn303/
H A Ddcn303_init.c36 dc->hwseq->funcs.dpp_pg_control = dcn303_dpp_pg_control; in dcn303_hw_sequencer_construct()
37 dc->hwseq->funcs.hubp_pg_control = dcn303_hubp_pg_control; in dcn303_hw_sequencer_construct()
38 dc->hwseq->funcs.dsc_pg_control = dcn303_dsc_pg_control; in dcn303_hw_sequencer_construct()
39 dc->hwseq->funcs.enable_power_gating_plane = dcn303_enable_power_gating_plane; in dcn303_hw_sequencer_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_init.c38 dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control; in dcn302_hw_sequencer_construct()
39 dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control; in dcn302_hw_sequencer_construct()
40 dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control; in dcn302_hw_sequencer_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c80 struct dce_hwseq *hws = dc->hwseq;
143 struct dce_hwseq *hws = dc->hwseq; in dcn35_init_hw()
532 dc->hwseq->funcs.edp_backlight_control && in dcn35_power_down_on_boot()
533 dc->hwseq->funcs.power_down && in dcn35_power_down_on_boot()
535 dc->hwseq->funcs.edp_backlight_control(edp_link, false); in dcn35_power_down_on_boot()
536 dc->hwseq->funcs.power_down(dc); in dcn35_power_down_on_boot()
544 dc->hwseq->funcs.power_down) { in dcn35_power_down_on_boot()
545 dc->hwseq->funcs.power_down(dc); in dcn35_power_down_on_boot()
624 struct dce_hwseq *hws = dc->hwseq; in dcn35_init_pipes()
896 struct dce_hwseq *hws = dc->hwseq; in dcn35_disable_plane()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c74 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power()
114 struct dce_hwseq *hws = dc->hwseq; in dcn31_init_hw()
127 hws->funcs.disable_vga(dc->hwseq); in dcn31_init_hw()
184 hws->funcs.enable_power_gating_plane(dc->hwseq, true); in dcn31_init_hw()
527 if (dc->hwseq) in dcn31_reset_back_end_for_pipe()
528 dc->hwseq->wa_state.skip_blank_stream = false; in dcn31_reset_back_end_for_pipe()
533 if (dc->hwseq) in dcn31_reset_back_end_for_pipe()
534 dc->hwseq->wa_state.skip_blank_stream = true; in dcn31_reset_back_end_for_pipe()
604 if (dc->hwseq) in dcn31_reset_back_end_for_pipe()
605 dc->hwseq->wa_state.skip_blank_stream = false; in dcn31_reset_back_end_for_pipe()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_vm_helper.c43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
59 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid); in dc_setup_vm_context()
H A Ddc_hw_sequencer.c741 struct dce_hwseq *hws = dc->hwseq; in hwss_build_fast_sequence()
948 struct dce_hwseq *hws = dc->hwseq; in hwss_execute_sequence()
2089 struct dce_hwseq *hws = dc->hwseq; in hwss_wait_for_all_blank_complete()
2620 struct dce_hwseq *hwseq = dc->hwseq; in hwss_update_force_pstate() local
2622 if (hwseq->funcs.update_force_pstate) in hwss_update_force_pstate()
2623 hwseq->funcs.update_force_pstate(dc, context); in hwss_update_force_pstate()
2935 struct dce_hwseq *hws = dc->hwseq; in hwss_dc_ip_request_cntl()
3025 struct dce_hwseq *hws = dc->hwseq; in hwss_mpc_update_mpcc()
H A Ddc.c1384 if (dc->hwseq->funcs.blank_pixel_data) in disable_dangling_plane()
1385 dc->hwseq->funcs.blank_pixel_data(dc, pipe, true); in disable_dangling_plane()
2162 if (dc->hwseq->funcs.wait_for_pipe_update_if_needed) { in dc_commit_state_no_check()
2168 dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, pipe, false); in dc_commit_state_no_check()
2245 if (dc->hwseq->funcs.set_wait_for_update_needed_for_pipe) { in dc_commit_state_no_check()
2248 dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe); in dc_commit_state_no_check()
4284 if (dc->hwseq->funcs.wait_for_pipe_update_if_needed) in commit_planes_for_stream()
4285 …dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type < UPDATE_TYPE… in commit_planes_for_stream()
4437 if (dc->hwseq->funcs.set_wait_for_update_needed_for_pipe && update_type == UPDATE_TYPE_FULL) { in commit_planes_for_stream()
4441 dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe_ctx); in commit_planes_for_stream()
[all …]
H A Ddc_resource.c403 kfree(dc->hwseq); in dc_destroy_resource_pool()
538 dc->hwseq = create_funcs->create_hwseq(ctx); in resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c139 struct dce_hwseq *hws = dc->hwseq; in dcn401_init_hw()
227 hws->funcs.enable_power_gating_plane(dc->hwseq, true); in dcn401_init_hw()
761 struct dce_hwseq *hws = dc->hwseq; in dcn401_enable_stream_timing()
820 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) in dcn401_enable_stream_timing()
821 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); in dcn401_enable_stream_timing()
1610 dc->hwseq->funcs.blank_pixel_data(dc, otg_master, true); in dcn401_update_odm()
1744 if (dc->hwseq->funcs.blank_pixel_data_sequence) in dcn401_update_odm_sequence()
1745 dc->hwseq->funcs.blank_pixel_data_sequence( in dcn401_update_odm_sequence()
1756 struct dce_hwseq *hws = link->dc->hwseq; in dcn401_unblank_stream()
2047 struct dce_hwseq *hws = dc->hwseq; in dcn401_reset_hw_ctx_wrap()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c394 struct dce_hwseq *hws = dc->hwseq; in dcn20_init_blank()
697 struct dce_hwseq *hws = dc->hwseq; in dcn20_plane_atomic_disable()
821 struct dce_hwseq *hws = dc->hwseq; in dcn20_enable_stream_timing()
904 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) in dcn20_enable_stream_timing()
905 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); in dcn20_enable_stream_timing()
1104 struct dce_hwseq *hws = dc->hwseq; in dcn20_set_input_transfer_func()
1303 dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx); in dcn20_enable_plane()
1468 if (dc->hwseq->funcs.perform_3dlut_wa_unlock) in dcn20_pipe_control_lock()
1469 dc->hwseq->funcs.perform_3dlut_wa_unlock(pipe); in dcn20_pipe_control_lock()
1669 struct dce_hwseq *hws = dc->hwseq; in dcn20_update_dchubp_dpp()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c256 struct dce_hwseq *hws = dc->hwseq; in log_mpc_crc()
1036 struct dce_hwseq *hws = dc->hwseq; in undo_DEGVIDCN10_253_wa()
1056 struct dce_hwseq *hws = dc->hwseq; in apply_DEGVIDCN10_253_wa()
1086 struct dce_hwseq *hws = dc->hwseq; in dcn10_bios_golden_init()
1132 if (!dc->hwseq->wa.false_optc_underflow) in false_optc_underflow_wa()
1445 struct dce_hwseq *hws = dc->hwseq; in dcn10_plane_atomic_disconnect()
1492 struct dce_hwseq *hws = dc->hwseq; in dcn10_plane_atomic_power_down()
1523 struct dce_hwseq *hws = dc->hwseq; in dcn10_plane_atomic_disable()
1556 struct dce_hwseq *hws = dc->hwseq; in dcn10_disable_plane()
1573 struct dce_hwseq *hws = dc->hwseq; in dcn10_init_pipes()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c533 struct dce_hwseq *hws = dc->hwseq; in dcn32_set_input_transfer_func()
731 struct dce_hwseq *hws = dc->hwseq; in dcn32_program_mall_pipe_config()
788 struct dce_hwseq *hws = dc->hwseq; in dcn32_init_hw()
805 hws->funcs.disable_vga(dc->hwseq); in dcn32_init_hw()
865 hws->funcs.enable_power_gating_plane(dc->hwseq, true); in dcn32_init_hw()
1188 dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true); in dcn32_update_odm()
1196 struct dce_hwseq *hws = stream->ctx->dc->hwseq; in dcn32_calculate_dccg_k1_k2_values()
1234 struct dce_hwseq *hws = dc->hwseq; in dcn32_calculate_pix_rate_divider()
1316 struct dce_hwseq *hws = link->dc->hwseq; in dcn32_unblank_stream()
1525 struct dce_hwseq *hws = dc->hwseq; in dcn32_update_dsc_pg()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1194 struct dce_hwseq *hws = link->dc->hwseq; in dce110_unblank_stream()
1212 struct dce_hwseq *hws = link->dc->hwseq; in dce110_blank_stream()
1578 struct dce_hwseq *hws = dc->hwseq; in dce110_apply_single_controller_ctx_to_hw()
1903 struct dce_hwseq *hws = dc->hwseq; in dce110_enable_accelerated_mode()
2449 struct dce_hwseq *hws = dc->hwseq; in dce110_apply_ctx_to_hw()
2482 dce_crtc_switch_to_clk_src(dc->hwseq, in dce110_apply_ctx_to_hw()
2497 if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) { in dce110_apply_ctx_to_hw()
2498 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired); in dce110_apply_ctx_to_hw()
2609 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); in program_surface_visibility()
2809 struct dce_hwseq *hws = dc->hwseq; in dce110_init_hw()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce112/
H A Ddce112_hwseq.c158 dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating; in dce112_hw_sequencer_construct()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c149 if (dce121_xgmi_enabled(ctx->dc->hwseq)) in dce121_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c53 struct dce_hwseq *hws = dc->hwseq; in dce_pipe_control_lock()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c320 struct dce_hwseq *hws = dc->hwseq; in dcn30_set_input_transfer_func()
644 struct dce_hwseq *hws = dc->hwseq; in dcn30_init_hw()
661 hws->funcs.disable_vga(dc->hwseq); in dcn30_init_hw()
728 hws->funcs.enable_power_gating_plane(dc->hwseq, true); in dcn30_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1226 struct dce_hwseq *hws = dc->hwseq; in get_pixel_clock_parameters()
2728 dc->hwseq->funcs.enable_power_gating_plane = NULL; in dcn20_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c1134 struct dce_hwseq *hws = dc->hwseq; in dce110_acquire_underlay()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h1782 struct dce_hwseq *hwseq; member