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Searched refs:hwseq (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c88 static bool gpu_addr_to_uma(struct dce_hwseq *hwseq, in gpu_addr_to_uma() argument
93 if (hwseq->fb_base.quad_part <= addr->quad_part && in gpu_addr_to_uma()
94 addr->quad_part < hwseq->fb_top.quad_part) { in gpu_addr_to_uma()
95 addr->quad_part -= hwseq->fb_base.quad_part; in gpu_addr_to_uma()
96 addr->quad_part += hwseq->fb_offset.quad_part; in gpu_addr_to_uma()
98 } else if (hwseq->fb_offset.quad_part <= addr->quad_part && in gpu_addr_to_uma()
99 addr->quad_part <= hwseq->uma_top.quad_part) { in gpu_addr_to_uma()
110 static void plane_address_in_gpu_space_to_uma(struct dce_hwseq *hwseq, in plane_address_in_gpu_space_to_uma() argument
115 gpu_addr_to_uma(hwseq, &addr->grph.addr); in plane_address_in_gpu_space_to_uma()
116 gpu_addr_to_uma(hwseq, &addr->grph.meta_addr); in plane_address_in_gpu_space_to_uma()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn303/
H A Ddcn303_init.c36 dc->hwseq->funcs.dpp_pg_control = dcn303_dpp_pg_control; in dcn303_hw_sequencer_construct()
37 dc->hwseq->funcs.hubp_pg_control = dcn303_hubp_pg_control; in dcn303_hw_sequencer_construct()
38 dc->hwseq->funcs.dsc_pg_control = dcn303_dsc_pg_control; in dcn303_hw_sequencer_construct()
39 dc->hwseq->funcs.enable_power_gating_plane = dcn303_enable_power_gating_plane; in dcn303_hw_sequencer_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_init.c38 dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control; in dcn302_hw_sequencer_construct()
39 dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control; in dcn302_hw_sequencer_construct()
40 dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control; in dcn302_hw_sequencer_construct()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_vm_helper.c43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
59 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid); in dc_setup_vm_context()
H A Ddc_hw_sequencer.c741 struct dce_hwseq *hws = dc->hwseq; in hwss_build_fast_sequence()
958 struct dce_hwseq *hws = dc->hwseq; in hwss_execute_sequence()
2112 struct dce_hwseq *hws = dc->hwseq; in hwss_wait_for_all_blank_complete()
2643 struct dce_hwseq *hwseq = dc->hwseq; in hwss_update_force_pstate() local
2645 if (hwseq->funcs.update_force_pstate) in hwss_update_force_pstate()
2646 hwseq->funcs.update_force_pstate(dc, context); in hwss_update_force_pstate()
2958 struct dce_hwseq *hws = dc->hwseq; in hwss_dc_ip_request_cntl()
3048 struct dce_hwseq *hws = dc->hwseq; in hwss_mpc_update_mpcc()
H A Ddc_resource.c410 kfree(dc->hwseq); in dc_destroy_resource_pool()
545 dc->hwseq = create_funcs->create_hwseq(ctx); in resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c139 struct dce_hwseq *hws = dc->hwseq; in dcn401_init_hw()
228 hws->funcs.enable_power_gating_plane(dc->hwseq, true); in dcn401_init_hw()
656 struct dce_hwseq *hws = dc->hwseq; in dcn401_enable_stream_timing()
715 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) in dcn401_enable_stream_timing()
716 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); in dcn401_enable_stream_timing()
1527 dc->hwseq->funcs.blank_pixel_data(dc, otg_master, true); in dcn401_update_odm()
1661 if (dc->hwseq->funcs.blank_pixel_data_sequence) in dcn401_update_odm_sequence()
1662 dc->hwseq->funcs.blank_pixel_data_sequence( in dcn401_update_odm_sequence()
1673 struct dce_hwseq *hws = link->dc->hwseq; in dcn401_unblank_stream()
1979 struct dce_hwseq *hws = dc->hwseq; in dcn401_reset_hw_ctx_wrap()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce112/
H A Ddce112_hwseq.c158 dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating; in dce112_hw_sequencer_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1261 struct dce_hwseq *hws = link->dc->hwseq; in dce110_unblank_stream()
1279 struct dce_hwseq *hws = link->dc->hwseq; in dce110_blank_stream()
1646 struct dce_hwseq *hws = dc->hwseq; in dce110_apply_single_controller_ctx_to_hw()
2000 struct dce_hwseq *hws = dc->hwseq; in dce110_enable_accelerated_mode()
2546 struct dce_hwseq *hws = dc->hwseq; in dce110_apply_ctx_to_hw()
2579 dce_crtc_switch_to_clk_src(dc->hwseq, in dce110_apply_ctx_to_hw()
2594 if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) { in dce110_apply_ctx_to_hw()
2595 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired); in dce110_apply_ctx_to_hw()
2718 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); in program_surface_visibility()
2920 struct dce_hwseq *hws = dc->hwseq; in dce110_init_hw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c149 if (dce121_xgmi_enabled(ctx->dc->hwseq)) in dce121_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c53 struct dce_hwseq *hws = dc->hwseq; in dce_pipe_control_lock()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1261 struct dce_hwseq *hws = dc->hwseq; in get_pixel_clock_parameters()
2787 dc->hwseq->funcs.enable_power_gating_plane = NULL; in dcn20_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c1140 struct dce_hwseq *hws = dc->hwseq; in dce110_acquire_underlay()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h1830 struct dce_hwseq *hwseq; member