Home
last modified time | relevance | path

Searched refs:hwirq (Results 1 – 25 of 217) sorted by relevance

123456789

/linux/Documentation/translations/zh_CN/core-api/irq/
H A Dirq-domain.rst33 提供任何对控制器本地IRQ(hwirq)号到Linux IRQ号空间的反向映射的支持。
35 irq_domain 库在 irq_alloc_desc*() API 的基础上增加了 hwirq 和 IRQ 号码
39 irq_domain还实现了从抽象的irq_fwspec结构体到hwirq号的转换（到目前为止是
50 在大多数情况下，irq_domain在开始时是空的，没有任何hwirq和IRQ号之间的映射。
52 irq_domain和一个hwirq号作为参数。 如果hwirq的映射还不存在，那么它将分配
53 一个新的Linux irq_desc，将其与hwirq关联起来，并调用.map()回调，这样驱动
58 - irq_resolve_mapping()返回一个指向给定域和hwirq号的irq_desc结构指针，
61 - irq_find_mapping()返回给定域和hwirq的Linux IRQ号，如果没有映射则返回0。
63 - generic_handle_domain_irq()处理一个由域和hwirq号描述的中断。
70 如果驱动程序有Linux的IRQ号或irq_data指针，并且需要知道相关的hwirq号（比
[all …]
/linux/drivers/irqchip/
H A Dirq-sp7021-intc.c81 static void sp_intc_assign_bit(u32 hwirq, void __iomem *base, bool value) in sp_intc_assign_bit() argument
87 offset = (hwirq / 32) * 4; in sp_intc_assign_bit()
93 mask |= BIT(hwirq % 32); in sp_intc_assign_bit()
95 mask &= ~BIT(hwirq % 32); in sp_intc_assign_bit()
102 u32 hwirq = d->hwirq; in sp_intc_ack_irq() local
104 if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_EDGE))) { // WORKAROUND in sp_intc_ack_irq()
105 sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, !TEST_STATE(hwirq, _IS_LOW)); in sp_intc_ack_irq()
106 ASSIGN_STATE(hwirq, _IS_ACTIVE, true); in sp_intc_ack_irq()
109 sp_intc_assign_bit(hwirq, REG_INTR_CLEAR, 1); in sp_intc_ack_irq()
114 sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 0); in sp_intc_mask_irq()
[all …]
H A Dirq-mchp-eic.c51 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
53 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
62 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
64 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
74 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
96 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
103 irq_set_irq_wake(eic->irqs[d->hwirq], on); in mchp_eic_irq_set_wake()
105 eic->wakeup_source |= BIT(d->hwirq); in mchp_eic_irq_set_wake()
107 eic->wakeup_source &= ~BIT(d->hwirq); in mchp_eic_irq_set_wake()
114 unsigned int hwirq; in mchp_eic_irq_suspend() local
[all …]
H A Dirq-mmp.c71 int hwirq; in icu_mask_ack_irq() local
74 hwirq = d->irq - data->virq_base; in icu_mask_ack_irq()
76 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
79 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
83 && (hwirq == data->clr_mfp_hwirq)) in icu_mask_ack_irq()
86 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq()
95 int hwirq; in icu_mask_irq() local
98 hwirq = d->irq - data->virq_base; in icu_mask_irq()
100 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
103 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
[all …]
H A Dirq-pruss-intc.c178 static void pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq) in pruss_intc_map() argument
186 intc->event_channel[hwirq].ref_count++; in pruss_intc_map()
188 ch = intc->event_channel[hwirq].value; in pruss_intc_map()
191 pruss_intc_update_cmr(intc, hwirq, ch); in pruss_intc_map()
193 reg_idx = hwirq / 32; in pruss_intc_map()
194 val = BIT(hwirq % 32); in pruss_intc_map()
208 hwirq, ch, host); in pruss_intc_map()
222 static void pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq) in pruss_intc_unmap() argument
229 ch = intc->event_channel[hwirq].value; in pruss_intc_unmap()
240 intc->event_channel[hwirq].ref_count--; in pruss_intc_unmap()
[all …]
H A Dirq-mvebu-sei.c61 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq()
63 writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)), in mvebu_sei_ack_irq()
70 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq()
76 reg |= BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_mask_irq()
84 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_unmask_irq()
90 reg &= ~BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_unmask_irq()
146 msg->data = data->hwirq + sei->caps->cp_range.first; in mvebu_sei_cp_compose_msi_msg()
201 unsigned long *hwirq, in mvebu_sei_ap_translate() argument
204 *hwirq = fwspec->param[0]; in mvebu_sei_ap_translate()
215 unsigned long hwirq; in mvebu_sei_ap_alloc() local
[all …]
H A Dirq-ls-extirq.c57 irq_hw_number_t hwirq = data->hwirq; in ls_extirq_set_type() local
61 mask = 1U << (31 - hwirq); in ls_extirq_set_type()
63 mask = 1U << hwirq; in ls_extirq_set_type()
104 irq_hw_number_t hwirq; in ls_extirq_domain_alloc() local
109 hwirq = fwspec->param[0]; in ls_extirq_domain_alloc()
110 if (hwirq >= priv->nirq) in ls_extirq_domain_alloc()
113 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &ls_extirq_chip, in ls_extirq_domain_alloc()
116 return irq_domain_alloc_irqs_parent(domain, virq, 1, &priv->map[hwirq]); in ls_extirq_domain_alloc()
141 u32 hwirq, intsize, j; in ls_extirq_parse_map() local
145 hwirq = be32_to_cpup(map); in ls_extirq_parse_map()
[all …]
H A Dirq-mbigen.c81 static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) in get_mbigen_vec_reg() argument
85 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_vec_reg()
86 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; in get_mbigen_vec_reg()
87 pin = hwirq % IRQS_PER_MBIGEN_NODE; in get_mbigen_vec_reg()
92 static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, in get_mbigen_type_reg() argument
97 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_type_reg()
98 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; in get_mbigen_type_reg()
99 irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE; in get_mbigen_type_reg()
107 static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq, in get_mbigen_clear_reg() argument
110 unsigned int ofst = (hwirq / 32) * 4; in get_mbigen_clear_reg()
[all …]
H A Dirq-xilinx-intc.c67 unsigned long mask = BIT(d->hwirq); in intc_enable_or_unmask()
69 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); in intc_enable_or_unmask()
85 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); in intc_disable_or_mask()
86 xintc_write(irqc, CIE, BIT(d->hwirq)); in intc_disable_or_mask()
93 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); in intc_ack()
94 xintc_write(irqc, IAR, BIT(d->hwirq)); in intc_ack()
100 unsigned long mask = BIT(d->hwirq); in intc_mask_ack()
102 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); in intc_mask_ack()
145 u32 hwirq = xintc_read(irqc, IVR); in xil_intc_irq_handler() local
147 if (hwirq == -1U) in xil_intc_irq_handler()
[all …]
H A Dirq-sni-exiu.c44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_ack()
58 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_eoi()
68 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); in exiu_irq_mask()
78 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_unmask()
89 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_enable()
91 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_enable()
103 val |= BIT(d->hwirq); in exiu_irq_set_type()
105 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
110 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
113 val |= BIT(d->hwirq); in exiu_irq_set_type()
[all …]
H A Dirq-riscv-intc.c54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
63 csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_unmask()
65 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
75 unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); in andes_intc_irq_mask()
77 if (d->hwirq < ANDES_SLI_CAUSE_BASE) in andes_intc_irq_mask()
85 unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); in andes_intc_irq_unmask()
87 if (d->hwirq < ANDES_SLI_CAUSE_BASE) in andes_intc_irq_unmask()
[all …]
H A Dirq-sifive-plic.c108 static void __plic_toggle(struct plic_handler *handler, int hwirq, int enable) in __plic_toggle() argument
111 u32 hwirq_mask = 1 << (hwirq % 32); in __plic_toggle()
112 int group = hwirq / 32; in __plic_toggle()
126 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) in plic_toggle() argument
131 __plic_toggle(handler, hwirq, enable); in plic_toggle()
143 plic_toggle(handler, d->hwirq, enable); in plic_irq_toggle()
151 writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_unmask()
158 writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_mask()
178 reg = handler->enable_base + (d->hwirq / 32) * sizeof(u32); in plic_irq_eoi()
179 enabled = readl(reg) & BIT(d->hwirq % 32); in plic_irq_eoi()
[all …]
H A Dirq-vf610-mscm-ir.c88 irq_hw_number_t hwirq = data->hwirq; in vf610_mscm_ir_enable() local
92 irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq)); in vf610_mscm_ir_enable()
98 chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq)); in vf610_mscm_ir_enable()
105 irq_hw_number_t hwirq = data->hwirq; in vf610_mscm_ir_disable() local
108 writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq)); in vf610_mscm_ir_disable()
128 irq_hw_number_t hwirq; in vf610_mscm_ir_domain_alloc() local
138 hwirq = fwspec->param[0]; in vf610_mscm_ir_domain_alloc()
140 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, in vf610_mscm_ir_domain_alloc()
162 unsigned long *hwirq, in vf610_mscm_ir_domain_translate() argument
167 *hwirq = fwspec->param[0]; in vf610_mscm_ir_domain_translate()
H A Dirq-mips-cpu.c42 set_c0_status(IE_SW0 << d->hwirq); in unmask_mips_irq()
48 clear_c0_status(IE_SW0 << d->hwirq); in mask_mips_irq()
71 clear_c0_cause(C_SW0 << d->hwirq); in mips_mt_cpu_irq_startup()
84 clear_c0_cause(C_SW0 << d->hwirq); in mips_mt_cpu_irq_ack()
93 irq_hw_number_t hwirq = irqd_to_hwirq(d); in mips_mt_send_ipi() local
104 write_vpe_c0_cause(read_vpe_c0_cause() | (C_SW0 << hwirq)); in mips_mt_send_ipi()
187 unsigned int i, hwirq; in mips_cpu_ipi_alloc() local
191 hwirq = find_first_zero_bit(state->allocated, 2); in mips_cpu_ipi_alloc()
192 if (hwirq == 2) in mips_cpu_ipi_alloc()
194 bitmap_set(state->allocated, hwirq, 1); in mips_cpu_ipi_alloc()
[all …]
H A Dirq-aspeed-vic.c110 unsigned int sidx = d->hwirq >> 5; in avic_ack_irq()
111 unsigned int sbit = 1u << (d->hwirq & 0x1f); in avic_ack_irq()
121 unsigned int sidx = d->hwirq >> 5; in avic_mask_irq()
122 unsigned int sbit = 1u << (d->hwirq & 0x1f); in avic_mask_irq()
130 unsigned int sidx = d->hwirq >> 5; in avic_unmask_irq()
131 unsigned int sbit = 1u << (d->hwirq & 0x1f); in avic_unmask_irq()
140 unsigned int sidx = d->hwirq >> 5; in avic_mask_ack_irq()
141 unsigned int sbit = 1u << (d->hwirq & 0x1f); in avic_mask_ack_irq()
160 irq_hw_number_t hwirq) in avic_map() argument
163 unsigned int sidx = hwirq >> 5; in avic_map()
[all …]
/linux/arch/powerpc/sysdev/
H A Dmpic_u3msi.c61 static u64 find_ht_magic_addr(struct pci_dev *pdev, unsigned int hwirq) in find_ht_magic_addr() argument
75 static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq) in find_u4_magic_addr() argument
97 return 0xf8004000 | (hwirq << 4); in find_u4_magic_addr()
105 irq_hw_number_t hwirq; in u3msi_teardown_msi_irqs() local
108 hwirq = virq_to_hw(entry->irq); in u3msi_teardown_msi_irqs()
112 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1); in u3msi_teardown_msi_irqs()
122 int hwirq; in u3msi_setup_msi_irqs() local
136 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1); in u3msi_setup_msi_irqs()
137 if (hwirq < 0) { in u3msi_setup_msi_irqs()
139 return hwirq; in u3msi_setup_msi_irqs()
[all …]
/linux/drivers/misc/rp1/
H A Drp1_pci.c45 static void msix_cfg_set(struct rp1_dev *rp1, unsigned int hwirq, u32 value) in msix_cfg_set() argument
47 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_SET + MSIX_CFG(hwirq)); in msix_cfg_set()
50 static void msix_cfg_clr(struct rp1_dev *rp1, unsigned int hwirq, u32 value) in msix_cfg_clr() argument
52 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq)); in msix_cfg_clr()
58 struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq]; in rp1_mask_irq()
66 struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq]; in rp1_unmask_irq()
74 unsigned int hwirq = (unsigned int)irqd->hwirq; in rp1_irq_set_type() local
78 dev_dbg(&rp1->pdev->dev, "MSIX IACK EN for IRQ %u\n", hwirq); in rp1_irq_set_type()
79 msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK_EN); in rp1_irq_set_type()
80 rp1->level_triggered_irq[hwirq] = true; in rp1_irq_set_type()
[all …]
/linux/arch/powerpc/platforms/85xx/
H A Dsocrates_fpga_pic.c110 unsigned int irq_line, hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_ack() local
113 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_ack()
117 mask |= (1 << (hwirq + 16)); in socrates_fpga_pic_ack()
125 unsigned int hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_mask() local
129 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_mask()
133 mask &= ~(1 << hwirq); in socrates_fpga_pic_mask()
141 unsigned int hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_mask_ack() local
145 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_mask_ack()
149 mask &= ~(1 << hwirq); in socrates_fpga_pic_mask_ack()
150 mask |= (1 << (hwirq + 16)); in socrates_fpga_pic_mask_ack()
[all …]
/linux/arch/powerpc/platforms/pasemi/
H A Dmsi.c61 irq_hw_number_t hwirq; in pasemi_msi_teardown_msi_irqs() local
66 hwirq = virq_to_hw(entry->irq); in pasemi_msi_teardown_msi_irqs()
70 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, ALLOC_CHUNK); in pasemi_msi_teardown_msi_irqs()
79 int hwirq; in pasemi_msi_setup_msi_irqs() local
95 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, in pasemi_msi_setup_msi_irqs()
97 if (hwirq < 0) { in pasemi_msi_setup_msi_irqs()
99 return hwirq; in pasemi_msi_setup_msi_irqs()
102 virq = irq_create_mapping(msi_mpic->irqhost, hwirq); in pasemi_msi_setup_msi_irqs()
105 hwirq); in pasemi_msi_setup_msi_irqs()
106 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, in pasemi_msi_setup_msi_irqs()
[all …]
/linux/arch/arm/mach-imx/
H A Dgpc.c91 unsigned int idx = d->hwirq / 32; in imx_gpc_irq_set_wake()
94 mask = 1 << d->hwirq % 32; in imx_gpc_irq_set_wake()
125 void imx_gpc_hwirq_unmask(unsigned int hwirq) in imx_gpc_hwirq_unmask() argument
130 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_unmask()
132 val &= ~(1 << hwirq % 32); in imx_gpc_hwirq_unmask()
136 void imx_gpc_hwirq_mask(unsigned int hwirq) in imx_gpc_hwirq_mask() argument
141 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_mask()
143 val |= 1 << (hwirq % 32); in imx_gpc_hwirq_mask()
149 imx_gpc_hwirq_unmask(d->hwirq); in imx_gpc_irq_unmask()
155 imx_gpc_hwirq_mask(d->hwirq); in imx_gpc_irq_mask()
[all …]
H A Davic.c52 static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type) in avic_set_irq_fiq() argument
56 if (hwirq >= AVIC_NUM_IRQS) in avic_set_irq_fiq()
59 if (hwirq < AVIC_NUM_IRQS / 2) { in avic_set_irq_fiq()
60 irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq); in avic_set_irq_fiq()
61 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL); in avic_set_irq_fiq()
63 hwirq -= AVIC_NUM_IRQS / 2; in avic_set_irq_fiq()
64 irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq); in avic_set_irq_fiq()
65 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH); in avic_set_irq_fiq()
86 int idx = d->hwirq >> 5; in avic_irq_suspend()
92 u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ? in avic_irq_suspend()
[all …]
/linux/arch/powerpc/sysdev/ge/
H A Dge_pic.c116 unsigned int hwirq = irqd_to_hwirq(d); in gef_pic_mask() local
121 mask &= ~(1 << hwirq); in gef_pic_mask()
137 unsigned int hwirq = irqd_to_hwirq(d); in gef_pic_unmask() local
142 mask |= (1 << hwirq); in gef_pic_unmask()
159 irq_hw_number_t hwirq) in gef_pic_host_map() argument
235 int hwirq; in gef_pic_get_irq() local
244 for (hwirq = GEF_PIC_NUM_IRQS - 1; hwirq > -1; hwirq--) { in gef_pic_get_irq()
245 if (active & (0x1 << hwirq)) in gef_pic_get_irq()
249 (irq_hw_number_t)hwirq); in gef_pic_get_irq()
/linux/drivers/pci/controller/
H A Dpcie-iproc-msi.c145 static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_group() argument
147 return (hwirq % msi->nr_irqs); in hwirq_to_group()
151 unsigned long hwirq) in iproc_msi_addr_offset() argument
154 return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE; in iproc_msi_addr_offset()
156 return hwirq_to_group(msi, hwirq) * sizeof(u32); in iproc_msi_addr_offset()
196 static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_cpu() argument
198 return (hwirq % msi->nr_cpus); in hwirq_to_cpu()
202 unsigned long hwirq) in hwirq_to_canonical_hwirq()
204 return (hwirq - hwirq_to_cpu(msi, hwirq)); in hwirq_to_canonical_hwirq()
215 curr_cpu = hwirq_to_cpu(msi, data->hwirq); in iproc_msi_irq_set_affinity()
[all …]
/linux/drivers/mailbox/
H A Dqcom-ipcc.c77 u32 hwirq; in qcom_ipcc_irq_fn() local
81 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); in qcom_ipcc_irq_fn()
82 if (hwirq == IPCC_NO_PENDING_IRQ) in qcom_ipcc_irq_fn()
85 virq = irq_find_mapping(ipcc->irq_domain, hwirq); in qcom_ipcc_irq_fn()
86 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR); in qcom_ipcc_irq_fn()
96 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); in qcom_ipcc_mask_irq() local
98 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE); in qcom_ipcc_mask_irq()
104 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); in qcom_ipcc_unmask_irq() local
106 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE); in qcom_ipcc_unmask_irq()
152 u32 hwirq; in qcom_ipcc_mbox_send_data() local
[all …]
/linux/drivers/gpio/
H A Dgpio-lpc18xx.c78 irq_hw_number_t hwirq = irqd_to_hwirq(d); in lpc18xx_gpio_pin_ic_mask() local
83 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
87 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
94 gpiochip_disable_irq(ic->gpio, hwirq); in lpc18xx_gpio_pin_ic_mask()
101 irq_hw_number_t hwirq = irqd_to_hwirq(d); in lpc18xx_gpio_pin_ic_unmask() local
103 gpiochip_enable_irq(ic->gpio, hwirq); in lpc18xx_gpio_pin_ic_unmask()
108 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_unmask()
112 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_unmask()
128 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_eoi()
143 lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true); in lpc18xx_gpio_pin_ic_set_type()
[all …]

123456789