Home
last modified time | relevance | path

Searched refs:hdp_clk_cntl (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dhdp_v5_2.c57 uint32_t hdp_clk_cntl; in hdp_v5_2_update_mem_power_gating() local
65 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_mem_power_gating()
69 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_2_update_mem_power_gating()
71 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_2_update_mem_power_gating()
73 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
132 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_2_update_mem_power_gating()
134 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_2_update_mem_power_gating()
136 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
142 uint32_t hdp_clk_cntl; in hdp_v5_2_update_medium_grain_clock_gating() local
147 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_medium_grain_clock_gating()
[all …]
H A Dhdp_v5_0.c45 uint32_t hdp_clk_cntl, hdp_clk_cntl1; in hdp_v5_0_update_mem_power_gating() local
53 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_mem_power_gating()
58 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_0_update_mem_power_gating()
60 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_0_update_mem_power_gating()
62 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_0_update_mem_power_gating()
129 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_0_update_mem_power_gating()
131 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_0_update_mem_power_gating()
133 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_0_update_mem_power_gating()
139 uint32_t hdp_clk_cntl; in hdp_v5_0_update_medium_grain_clock_gating() local
144 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_medium_grain_clock_gating()
[all …]
H A Dhdp_v6_0.c36 uint32_t hdp_clk_cntl; in hdp_v6_0_update_clock_gating() local
45 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1); in hdp_v6_0_update_clock_gating()
47 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v6_0_update_clock_gating()
52 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v6_0_update_clock_gating()
55 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
57 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
117 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v6_0_update_clock_gating()
120 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
122 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
H A Dhdp_v7_0.c33 uint32_t hdp_clk_cntl, hdp_clk_cntl1; in hdp_v7_0_update_clock_gating() local
41 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL); in hdp_v7_0_update_clock_gating()
46 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v7_0_update_clock_gating()
48 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()
108 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v7_0_update_clock_gating()
110 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()