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Searched refs:hcr (Results 1 – 18 of 18) sorted by relevance

/linux/arch/arm64/kvm/vgic/
H A Dvgic-v3-nested.c182 u64 reg = 0, hcr, vmcr; in vgic_v3_get_misr() local
184 hcr = __vcpu_sys_reg(vcpu, ICH_HCR_EL2); in vgic_v3_get_misr()
199 if ((hcr & ICH_HCR_EL2_LRENPIE) && FIELD_GET(ICH_HCR_EL2_EOIcount_MASK, hcr)) in vgic_v3_get_misr()
202 if ((hcr & ICH_HCR_EL2_NPIE) && !mi_state.pend) in vgic_v3_get_misr()
205 if ((hcr & ICH_HCR_EL2_VGrp0EIE) && (vmcr & ICH_VMCR_ENG0_MASK)) in vgic_v3_get_misr()
208 if ((hcr & ICH_HCR_EL2_VGrp0DIE) && !(vmcr & ICH_VMCR_ENG0_MASK)) in vgic_v3_get_misr()
211 if ((hcr & ICH_HCR_EL2_VGrp1EIE) && (vmcr & ICH_VMCR_ENG1_MASK)) in vgic_v3_get_misr()
214 if ((hcr & ICH_HCR_EL2_VGrp1DIE) && !(vmcr & ICH_VMCR_ENG1_MASK)) in vgic_v3_get_misr()
H A Dvgic-v3.c844 u64 hcr = 0; in kvm_compute_ich_hcr_trap_bits() local
862 hcr |= ICH_HCR_EL2_TALL0; in kvm_compute_ich_hcr_trap_bits()
864 hcr |= ICH_HCR_EL2_TALL1; in kvm_compute_ich_hcr_trap_bits()
866 hcr |= ICH_HCR_EL2_TC; in kvm_compute_ich_hcr_trap_bits()
868 hcr |= ICH_HCR_EL2_TDIR; in kvm_compute_ich_hcr_trap_bits()
876 (u16)hcr, in kvm_compute_ich_hcr_trap_bits()
H A Dvgic.h172 u64 hcr; in vgic_ich_hcr_trap_bits() local
178 : "=r" (hcr)); in vgic_ich_hcr_trap_bits()
180 return hcr; in vgic_ich_hcr_trap_bits()
/linux/arch/arm64/include/asm/
H A Dhardirq.h22 u64 hcr; member
58 ___ctx->hcr = ___hcr; \
70 ___hcr = ___ctx->hcr; \
/linux/drivers/usb/serial/
H A Dark3116.c67 __u32 hcr; /* handshake control register (0x8) member
145 priv->hcr = 0; in ark3116_port_probe()
200 __u8 lcr, hcr, eval; in ark3116_set_termios() local
215 hcr = (cflag & CRTSCTS) ? 0x03 : 0x00; in ark3116_set_termios()
246 __func__, hcr, lcr, quot); in ark3116_set_termios()
249 if (priv->hcr != hcr) { in ark3116_set_termios()
250 priv->hcr = hcr; in ark3116_set_termios()
251 ark3116_write_reg(serial, 0x8, hcr); in ark3116_set_termios()
/linux/arch/arm64/kvm/hyp/include/hyp/
H A Dswitch.h353 static inline void ___activate_traps(struct kvm_vcpu *vcpu, u64 hcr) in ___activate_traps() argument
356 hcr |= HCR_TVM; in ___activate_traps()
358 write_sysreg_hcr(hcr); in ___activate_traps()
360 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE)) { in ___activate_traps()
391 u64 *hcr; in ___deactivate_traps() local
394 hcr = __ctxt_sys_reg(&vcpu->arch.ctxt, HCR_EL2); in ___deactivate_traps()
396 hcr = &vcpu->arch.hcr_el2; in ___deactivate_traps()
407 if (*hcr & HCR_VSE) { in ___deactivate_traps()
408 *hcr &= ~HCR_VSE; in ___deactivate_traps()
409 *hcr |= read_sysreg(hcr_el2) & HCR_VSE; in ___deactivate_traps()
/linux/arch/arm64/kvm/hyp/vhe/
H A Dswitch.c54 u64 guest_hcr, hcr = vcpu->arch.hcr_el2; in __compute_hcr() local
57 return hcr; in __compute_hcr()
68 hcr |= HCR_NV | HCR_NV2 | HCR_AT | HCR_TTLB; in __compute_hcr()
71 hcr |= HCR_NV1; in __compute_hcr()
110 return hcr | (guest_hcr & ~NV_HCR_GUEST_EXCLUDE); in __compute_hcr()
/linux/drivers/infiniband/hw/mthca/
H A Dmthca_cmd.c194 return readl(dev->hcr + HCR_STATUS_OFFSET) & in go_bit()
257 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); in mthca_cmd_post_hcr()
258 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); in mthca_cmd_post_hcr()
259 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4); in mthca_cmd_post_hcr()
260 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4); in mthca_cmd_post_hcr()
261 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4); in mthca_cmd_post_hcr()
262 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4); in mthca_cmd_post_hcr()
270 op), dev->hcr + 6 * 4); in mthca_cmd_post_hcr()
367 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 | in mthca_cmd_poll()
369 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4)); in mthca_cmd_poll()
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H A Dmthca_dev.h322 void __iomem *hcr; member
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dcmd.c425 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET); in cmd_pending()
437 u32 __iomem *hcr = cmd->hcr; in mlx4_cmd_post() local
482 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0); in mlx4_cmd_post()
483 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1); in mlx4_cmd_post()
484 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2); in mlx4_cmd_post()
485 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3); in mlx4_cmd_post()
486 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4); in mlx4_cmd_post()
487 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5); in mlx4_cmd_post()
496 op), hcr + 6); in mlx4_cmd_post()
581 void __iomem *hcr = priv->cmd.hcr; in mlx4_cmd_poll() local
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H A Dmlx4.h632 void __iomem *hcr; member
/linux/drivers/atm/
H A Dfore200e.c452 if (irq_posted && (readl(fore200e->regs.pca.hcr) & PCA200E_HCR_OUTFULL)) { in fore200e_pca_irq_check()
464 writel(PCA200E_HCR_CLRINTR, fore200e->regs.pca.hcr); in fore200e_pca_irq_ack()
471 writel(PCA200E_HCR_RESET, fore200e->regs.pca.hcr); in fore200e_pca_reset()
473 writel(0, fore200e->regs.pca.hcr); in fore200e_pca_reset()
491 fore200e->regs.pca.hcr = fore200e->virt_base + PCA200E_HCR_OFFSET; in fore200e_pca_map()
641 u32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY; in fore200e_sba_irq_enable() local
642 fore200e->bus->write(hcr | SBA200E_HCR_INTR_ENA, fore200e->regs.sba.hcr); in fore200e_sba_irq_enable()
647 return fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_INTR_REQ; in fore200e_sba_irq_check()
652 u32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY; in fore200e_sba_irq_ack() local
653 fore200e->bus->write(hcr | SBA200E_HCR_INTR_CLR, fore200e->regs.sba.hcr); in fore200e_sba_irq_ack()
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H A Dfore200e.h773 volatile u32 __iomem * hcr; /* address of host control register */ member
782 u32 __iomem *hcr; /* address of host control register */ member
/linux/arch/arm64/kvm/
H A Dat.c141 u64 hcr, sctlr, tcr, tg, ps, ia_bits, ttbr; in setup_s1_walk() local
148 hcr = __vcpu_sys_reg(vcpu, HCR_EL2); in setup_s1_walk()
149 wi->s2 = wi->regime == TR_EL10 && (hcr & (HCR_VM | HCR_DC)); in setup_s1_walk()
153 hcr = 0; in setup_s1_walk()
248 if (hcr & (HCR_DC | HCR_TGE)) { in setup_s1_walk()
1496 u64 val, hcr; in __kvm_at_s1e2() local
1499 val = hcr = read_sysreg(hcr_el2); in __kvm_at_s1e2()
1531 write_sysreg_hcr(hcr); in __kvm_at_s1e2()
H A Dnested.c657 u64 vttbr, vtcr, hcr; in lookup_s2_mmu() local
663 hcr = vcpu_read_sys_reg(vcpu, HCR_EL2); in lookup_s2_mmu()
665 nested_stage2_enabled = hcr & HCR_VM; in lookup_s2_mmu()
1867 unsigned long *hcr = vcpu_hcr(vcpu); in kvm_nested_sync_hwstate() local
1876 if (unlikely(__test_and_clear_bit(__ffs(HCR_VSE), hcr))) in kvm_nested_sync_hwstate()
H A Darm.c1363 unsigned long *hcr; in vcpu_interrupt_line() local
1370 hcr = vcpu_hcr(vcpu); in vcpu_interrupt_line()
1372 set = test_and_set_bit(bit_index, hcr); in vcpu_interrupt_line()
1374 set = test_and_clear_bit(bit_index, hcr); in vcpu_interrupt_line()
H A Dmmu.c2539 unsigned long hcr = *vcpu_hcr(vcpu); in kvm_set_way_flush() local
2550 if (!(hcr & HCR_TVM)) { in kvm_set_way_flush()
2554 *vcpu_hcr(vcpu) = hcr | HCR_TVM; in kvm_set_way_flush()
/linux/arch/arm64/kvm/hyp/
H A Dvgic-v3-sr.c795 u32 hcr; in __vgic_v3_bump_eoicount() local
797 hcr = read_gicreg(ICH_HCR_EL2); in __vgic_v3_bump_eoicount()
798 hcr += 1 << ICH_HCR_EL2_EOIcount_SHIFT; in __vgic_v3_bump_eoicount()
799 write_gicreg(hcr, ICH_HCR_EL2); in __vgic_v3_bump_eoicount()