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Searched refs:h_taps (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c218 if (in_taps->h_taps == 0) { in dpp201_get_optimal_number_of_taps()
220 scl_data->taps.h_taps = 8; in dpp201_get_optimal_number_of_taps()
222 scl_data->taps.h_taps = 4; in dpp201_get_optimal_number_of_taps()
224 scl_data->taps.h_taps = in_taps->h_taps; in dpp201_get_optimal_number_of_taps()
253 scl_data->taps.h_taps = 1; in dpp201_get_optimal_number_of_taps()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_transform.c122 if (data->taps.h_taps + data->taps.v_taps <= 2) { in setup_scaling_configuration()
132 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, in setup_scaling_configuration()
156 if (data->taps.h_taps + data->taps.v_taps <= 2) { in dce60_setup_scaling_configuration()
168 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, in dce60_setup_scaling_configuration()
297 dc_fixpt_from_int(data->taps.h_taps + 1)), in calculate_inits()
443 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); in dce_transform_set_scaler()
467 data->taps.h_taps, in dce_transform_set_scaler()
472 data->taps.h_taps, in dce_transform_set_scaler()
530 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); in dce60_transform_set_scaler()
552 data->taps.h_taps, in dce60_transform_set_scaler()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c420 plane->composition.scaler_info.plane0.h_taps = 1; in populate_dml21_dummy_plane_cfg()
422 plane->composition.scaler_info.plane1.h_taps = 0; in populate_dml21_dummy_plane_cfg()
551 if (!scaler_data->taps.h_taps) { in populate_dml21_plane_config_from_plane_state()
561 if ((scaler_data->taps.h_taps > 1) || (scaler_data->taps.v_taps > 1) || in populate_dml21_plane_config_from_plane_state()
584 if (!scaler_data->taps.h_taps) { in populate_dml21_plane_config_from_plane_state()
585 plane->composition.scaler_info.plane0.h_taps = 1; in populate_dml21_plane_config_from_plane_state()
586 plane->composition.scaler_info.plane1.h_taps = 1; in populate_dml21_plane_config_from_plane_state()
588 plane->composition.scaler_info.plane0.h_taps = scaler_data->taps.h_taps; in populate_dml21_plane_config_from_plane_state()
589 plane->composition.scaler_info.plane1.h_taps = scaler_data->taps.h_taps_c; in populate_dml21_plane_config_from_plane_state()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_dscl.c295 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 in dpp1_dscl_set_scl_filter()
297 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter()
317 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter()
338 dpp, scl_data->taps.h_taps, in dpp1_dscl_set_scl_filter()
690 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, in dpp1_dscl_set_scaler_manual_scale()
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_transform_v.c165 set_reg_field_value(value, data->taps.h_taps - 1, in setup_scaling_configuration()
176 if (data->taps.h_taps + data->taps.v_taps > 2) { in setup_scaling_configuration()
560 coeffs_h = get_filter_coeffs_64p(data->taps.h_taps, data->ratios.horz); in dce110_xfmv_set_scaler()
583 data->taps.h_taps, in dce110_xfmv_set_scaler()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c453 if (in_taps->h_taps == 0) { in dpp3_get_optimal_number_of_taps()
455 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); in dpp3_get_optimal_number_of_taps()
457 scl_data->taps.h_taps = 4; in dpp3_get_optimal_number_of_taps()
459 scl_data->taps.h_taps = in_taps->h_taps; in dpp3_get_optimal_number_of_taps()
528 scl_data->taps.h_taps = 1; in dpp3_get_optimal_number_of_taps()
/linux/drivers/gpu/drm/amd/display/dc/sspl/
H A Ddc_spl_isharp_filters.c550 SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p(data->taps.h_taps)); in SPL_NAMESPACE()
/linux/drivers/gpu/drm/amd/display/dc/basics/
H A Ddce_calcs.c380 data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); in calculate_bandwidth()
381 data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); in calculate_bandwidth()
434 data->h_taps[i] = bw_int_to_fixed(1); in calculate_bandwidth()
524 if (bw_mtn(data->hsr[i], data->h_taps[i])) { in calculate_bandwidth()
528 …sr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixe… in calculate_bandwidth()
1256 …data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_t… in calculate_bandwidth()
1704 …data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_t… in calculate_bandwidth()
2828 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2884 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2931 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
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H A Dcalcs_logger.h430 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_taps[%d]:%d", i, bw_fixed_to_int(data->h_taps[i])); in print_bw_calcs_data()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb_scl.c728 uint32_t h_taps_luma = num_taps.h_taps; in dwb_program_horz_scalar()
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Ddce_calcs.h396 struct bw_fixed h_taps[maximum_number_of_surfaces]; member
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h719 uint32_t h_taps; member
H A Ddc.h2995 uint32_t h_taps; /* SCL_TAP_CONTROL->SCL_H_NUM_TAPS from taps.h_taps */ member
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c8033 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps != 1.0 in dml_core_mode_support()
8038 …].composition.scaler_info.plane0.h_taps < 1.0 || display_cfg->plane_descriptors[k].composition.sca… in dml_core_mode_support()
8039 ….composition.scaler_info.plane0.h_taps > 1.0 && (display_cfg->plane_descriptors[k].composition.sca… in dml_core_mode_support()
8042 …caler_info.plane0.h_ratio > display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps in dml_core_mode_support()
8046 …k].composition.scaler_info.plane1.h_taps < 1 || display_cfg->plane_descriptors[k].composition.scal… in dml_core_mode_support()
8047 …k].composition.scaler_info.plane1.h_taps > 1 && display_cfg->plane_descriptors[k].composition.scal… in dml_core_mode_support()
8050 …er_info.plane1.h_ratio > display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps || in dml_core_mode_support()
8151 …ay_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps > (unsigned int) m… in dml_core_mode_support()
8153 …am_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps in dml_core_mode_support()
8155 …tream[0].h_taps > 2.0 && ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].strea… in dml_core_mode_support()
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/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
1012 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; in dcn_validate_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c1344 data->taps.h_taps, in calculate_inits_and_viewports()
1622 pipe_ctx->plane_res.scl_data.taps.h_taps != temp.h_taps || in resource_build_scaling_params()
H A Ddc.c6797 …state->dpp[i].h_taps = dscl_data->taps.h_taps + 1; // dscl_prog_data.taps stores (taps - 1), so ad… in dc_capture_register_software_state()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c10679 wb_info->dwb_params.scaler_taps.h_taps = 1; in dm_set_writeback()