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Searched refs:gpu_rmw (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/msm/adreno/
H A Da5xx_gpu.c796 gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); in a5xx_hw_init()
805 gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); in a5xx_hw_init()
827 gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, (1 << 11), 0); in a5xx_hw_init()
845 gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, (1 << 10)); in a5xx_hw_init()
915 gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, BIT(23)); in a5xx_hw_init()
916 gpu_rmw(gpu, REG_A5XX_HLSQ_DBG_ECO_CNTL, BIT(18), 0); in a5xx_hw_init()
1368 gpu_rmw(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0xff, 0); in a5xx_pm_resume()
H A Da6xx_gpu_state.c934 gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 3); in a7xx_get_shader_block()
964 gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 0); in a7xx_get_shader_block()
1617 gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, 0, BIT(2)); in a7xx_get_indexed_registers()
1619 gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, 0, BIT(2)); in a7xx_get_indexed_registers()
1626 gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(2), 0); in a7xx_get_indexed_registers()
1628 gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, BIT(2), 0); in a7xx_get_indexed_registers()
H A Da6xx_gpu.c1426 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); in hw_init()
1432 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(11), BIT(11)); in hw_init()
1989 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | in a6xx_llc_activate()
2026 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); in a6xx_llc_activate()
H A Da8xx_gpu.c231 gpu_rmw(gpu, REG_A6XX_GBIF_CX_CONFIG, BIT(0), 0); in a8xx_set_hwcg()
H A Da6xx_gmu.c1039 gpu_rmw(gpu, REG_A6XX_GBIF_CX_CONFIG, GENMASK(31, 29), in a6xx_gmu_fw_start()
/linux/drivers/gpu/drm/msm/
H A Dmsm_gpu.h660 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) in gpu_rmw() function