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Searched refs:gmu (Results 1 – 25 of 29) sorted by relevance

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/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gmu.c20 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault() argument
22 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fault()
27 gmu->hung = true; in a6xx_gmu_fault()
38 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
41 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
42 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
45 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
47 a6xx_gmu_fault(gmu); in a6xx_gmu_irq()
51 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); in a6xx_gmu_irq()
54 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
[all …]
H A Da6xx_gpu.c25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
496 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg() local
517 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, in a6xx_set_hwcg()
519 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, in a6xx_set_hwcg()
521 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, in a6xx_set_hwcg()
551 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
558 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
1041 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in hw_init() local
1048 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
1071 a6xx_sptprac_enable(gmu); in hw_init()
[all …]
H A Da6xx_gpu.h80 struct a6xx_gmu gmu; member
242 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
244 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
246 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
247 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
H A Da6xx_gpu_state.c155 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
1181 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers() local
1201 val = gmu_read_rscc(gmu, offset); in _a6xx_get_gmu_registers()
1203 val = gmu_read(gmu, offset); in _a6xx_get_gmu_registers()
1230 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_get_gmu_registers()
1268 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_snapshot_gmu_hfi_history() local
1271 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history)); in a6xx_snapshot_gmu_hfi_history()
1273 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) { in a6xx_snapshot_gmu_hfi_history()
1274 struct a6xx_hfi_queue *queue = &gmu->queues[i]; in a6xx_snapshot_gmu_hfi_history()
1577 a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log); in a6xx_gpu_state_get()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8350.dtsi1909 qcom,gmu = <&gmu>;
1974 gmu: gmu@3d6a000 { label
1975 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1980 reg-names = "gmu", "rscc", "gmu_pdc";
1984 interrupt-names = "hfi", "gmu";
1993 clock-names = "gmu",
H A Dqcm2290.dtsi1451 "gmu",
1462 qcom,gmu = <&gmu_wrapper>;
1531 gmu_wrapper: gmu@596a000 {
1532 compatible = "qcom,adreno-gmu-wrapper";
1534 reg-names = "gmu";
H A Dsm8150-mtp.dts353 &gmu {
H A Dsm8150.dtsi2253 qcom,gmu = <&gmu>;
2306 gmu: gmu@2c6a000 { label
2307 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2312 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2316 interrupt-names = "hfi", "gmu";
2323 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dsm8250-hdk.dts368 &gmu {
H A Dsm6115.dtsi1705 "gmu",
1713 qcom,gmu = <&gmu_wrapper>;
1779 gmu_wrapper: gmu@596a000 {
1780 compatible = "qcom,adreno-gmu-wrapper";
1782 reg-names = "gmu";
H A Dsdm845-xiaomi-beryllium-common.dtsi242 &gmu {
H A Dx1e80100.dtsi537 pld_gmu_mem: pld-gmu@81f36000 {
3325 qcom,gmu = <&gmu>;
3396 gmu: gmu@3d6a000 { label
3397 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
3401 reg-names = "gmu", "rscc", "gmu_pdc";
3405 interrupt-names = "hfi", "gmu";
3415 "gmu",
H A Dsm8550.dtsi2114 qcom,gmu = <&gmu>;
2169 gmu: gmu@3d6a000 { label
2170 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2174 reg-names = "gmu", "rscc", "gmu_pdc";
2178 interrupt-names = "hfi", "gmu";
2188 "gmu",
H A Dsm8650.dtsi2636 qcom,gmu = <&gmu>;
2706 gmu: gmu@3d6a000 { label
2707 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
2711 reg-names = "gmu", "rscc", "gmu_pdc";
2715 interrupt-names = "hfi", "gmu";
2725 "gmu",
H A Dsm8150-hdk.dts374 &gmu {
H A Dsm8250.dtsi2932 qcom,gmu = <&gmu>;
2991 gmu: gmu@3d6a000 { label
2992 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2998 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
3002 interrupt-names = "hfi", "gmu";
3009 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dsdm845-shift-axolotl.dts422 &gmu {
H A Dsdm845-xiaomi-polaris.dts384 &gmu {
H A Dsm8250-xiaomi-pipa.dts473 &gmu {
H A Dsdm845-mtp.dts417 &gmu {
H A Dsdm850-lenovo-yoga-c630.dts358 &gmu {
H A Dsa8295p-adp.dts342 &gmu {
H A Dsdm845-sony-xperia-tama.dtsi418 &gmu {
H A Dsm8250-xiaomi-elish-common.dtsi474 &gmu {
H A Dsm8250-mtp.dts481 &gmu {

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