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Searched refs:gmc (Results 1 – 25 of 63) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gmc.c46 return adev->gmc.xgmi.connected_to_cpu || amdgpu_virt_xgmi_migrate_enabled(adev); in amdgpu_gmc_is_pdb0_enabled()
61 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; in amdgpu_gmc_pdb0_alloc()
62 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; in amdgpu_gmc_pdb0_alloc()
75 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
79 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); in amdgpu_gmc_pdb0_alloc()
83 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_gmc_pdb0_alloc()
86 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); in amdgpu_gmc_pdb0_alloc()
90 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
94 amdgpu_bo_unpin(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
96 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
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H A Dgmc_v9_0.c696 adev->gmc.vm_fault.num_types = 1; in gmc_v9_0_set_irq_funcs()
697 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; in gmc_v9_0_set_irq_funcs()
700 !adev->gmc.xgmi.connected_to_cpu && in gmc_v9_0_set_irq_funcs()
701 !adev->gmc.is_app_apu) { in gmc_v9_0_set_irq_funcs()
702 adev->gmc.ecc_irq.num_types = 1; in gmc_v9_0_set_irq_funcs()
703 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; in gmc_v9_0_set_irq_funcs()
811 spin_lock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
873 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
1026 if (!adev->gmc.translate_further) in gmc_v9_0_get_vm_pde()
1080 adev->gmc.xgmi.connected_to_cpu) in gmc_v9_0_get_coherence_flags()
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H A Dgfxhub_v1_1.c88 if (max_region || adev->gmc.xgmi.connected_to_cpu) { in gfxhub_v1_1_get_xgmi_info()
89 adev->gmc.xgmi.num_physical_nodes = max_region + 1; in gfxhub_v1_1_get_xgmi_info()
91 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) in gfxhub_v1_1_get_xgmi_info()
95 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
99 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
104 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) in gfxhub_v1_1_get_xgmi_info()
107 adev->gmc.xgmi.node_segment_size = seg_size; in gfxhub_v1_1_get_xgmi_info()
H A Dmmhub_v4_2_0.c84 if (!adev->gmc.xgmi.connected_to_cpu) in mmhub_v4_2_0_get_xgmi_info()
98 adev->gmc.xgmi.num_physical_nodes = max_region + 1; in mmhub_v4_2_0_get_xgmi_info()
100 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) in mmhub_v4_2_0_get_xgmi_info()
103 adev->gmc.xgmi.physical_node_id = in mmhub_v4_2_0_get_xgmi_info()
106 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) in mmhub_v4_2_0_get_xgmi_info()
109 adev->gmc.xgmi.node_segment_size = seg_size; in mmhub_v4_2_0_get_xgmi_info()
176 if (adev->gmc.pdb0_bo) in mmhub_v4_2_0_mid_init_gart_aperture_regs()
177 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in mmhub_v4_2_0_mid_init_gart_aperture_regs()
184 if (adev->gmc.pdb0_bo) { in mmhub_v4_2_0_mid_init_gart_aperture_regs()
187 (u32)(adev->gmc.fb_start >> 12)); in mmhub_v4_2_0_mid_init_gart_aperture_regs()
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H A Dmmhub_v1_0.c48 adev->gmc.fb_start = base; in mmhub_v1_0_get_fb_location()
49 adev->gmc.fb_end = top; in mmhub_v1_0_get_fb_location()
75 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
77 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
80 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
82 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v1_0_init_system_aperture_regs()
93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v1_0_init_system_aperture_regs()
97 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v1_0_init_system_aperture_regs()
109 max((adev->gmc.fb_end >> 18) + 0x1, in mmhub_v1_0_init_system_aperture_regs()
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H A Dgfxhub_v12_0.c148 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v12_0_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v12_0_init_gart_aperture_regs()
153 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v12_0_init_gart_aperture_regs()
155 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v12_0_init_gart_aperture_regs()
164 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v12_0_init_system_aperture_regs()
165 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v12_0_init_system_aperture_regs()
169 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v12_0_init_system_aperture_regs()
171 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v12_0_init_system_aperture_regs()
174 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start in gfxhub_v12_0_init_system_aperture_regs()
242 if (adev->gmc.translate_further) { in gfxhub_v12_0_init_cache_regs()
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H A Dgfxhub_v11_5_0.c145 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v11_5_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v11_5_0_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v11_5_0_init_gart_aperture_regs()
152 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v11_5_0_init_gart_aperture_regs()
160 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v11_5_0_init_system_aperture_regs()
161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v11_5_0_init_system_aperture_regs()
165 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v11_5_0_init_system_aperture_regs()
168 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v11_5_0_init_system_aperture_regs()
237 if (adev->gmc.translate_further) { in gfxhub_v11_5_0_init_cache_regs()
364 adev->gmc.vram_start >> 24); in gfxhub_v11_5_0_gart_enable()
[all …]
H A Dgfxhub_v3_0.c140 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
142 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
156 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_init_system_aperture_regs()
157 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_init_system_aperture_regs()
162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v3_0_init_system_aperture_regs()
164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v3_0_init_system_aperture_regs()
234 if (adev->gmc.translate_further) { in gfxhub_v3_0_init_cache_regs()
361 adev->gmc.vram_start >> 24); in gfxhub_v3_0_gart_enable()
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H A Dgfxhub_v2_0.c141 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
143 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
146 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
148 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_0_init_system_aperture_regs()
159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_0_init_system_aperture_regs()
163 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
165 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
233 if (adev->gmc.translate_further) { in gfxhub_v2_0_init_cache_regs()
314 !adev->gmc.noretry); in gfxhub_v2_0_setup_vmid_config()
H A Dmmhub_v2_3.c131 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
133 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
136 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
138 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
148 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_3_init_system_aperture_regs()
149 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_3_init_system_aperture_regs()
153 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v2_3_init_system_aperture_regs()
155 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v2_3_init_system_aperture_regs()
219 if (adev->gmc.translate_further) { in mmhub_v2_3_init_cache_regs()
304 !adev->gmc.noretry); in mmhub_v2_3_setup_vmid_config()
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H A Dgfxhub_v3_0_3.c143 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v3_0_3_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v3_0_3_init_gart_aperture_regs()
148 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v3_0_3_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v3_0_3_init_gart_aperture_regs()
162 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_3_init_system_aperture_regs()
163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_3_init_system_aperture_regs()
167 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v3_0_3_init_system_aperture_regs()
169 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v3_0_3_init_system_aperture_regs()
239 if (adev->gmc.translate_further) { in gfxhub_v3_0_3_init_cache_regs()
H A Damdgpu_ttm.c138 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && in amdgpu_evict_flags()
150 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; in amdgpu_evict_flags()
237 *addr = amdgpu_compute_gart_address(&adev->gmc, entity, window); in amdgpu_ttm_map_buffer()
474 if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size) in amdgpu_res_cpu_visible()
641 mem->bus.offset += adev->gmc.aper_base; in amdgpu_ttm_io_mem_reserve()
676 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; in amdgpu_ttm_io_mem_pfn()
692 return adev->gmc.gart_start; in amdgpu_ttm_domain_start()
694 return adev->gmc.vram_start; in amdgpu_ttm_domain_start()
992 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; in amdgpu_ttm_alloc_gart()
1178 if (adev->gmc.mem_partitions && abo->xcp_id >= 0) in amdgpu_ttm_tt_create()
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H A Dmmhub_v3_0_2.c149 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_0_2_init_gart_aperture_regs()
151 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_0_2_init_gart_aperture_regs()
154 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_0_2_init_gart_aperture_regs()
156 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_0_2_init_gart_aperture_regs()
166 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
177 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_0_2_init_system_aperture_regs()
179 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_0_2_init_system_aperture_regs()
251 if (adev->gmc.translate_further) { in mmhub_v3_0_2_init_cache_regs()
H A Dmmhub_v4_1_0.c142 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v4_1_0_init_gart_aperture_regs()
144 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v4_1_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v4_1_0_init_gart_aperture_regs()
149 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v4_1_0_init_gart_aperture_regs()
167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v4_1_0_init_system_aperture_regs()
168 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v4_1_0_init_system_aperture_regs()
172 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v4_1_0_init_system_aperture_regs()
174 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v4_1_0_init_system_aperture_regs()
177 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start + in mmhub_v4_1_0_init_system_aperture_regs()
246 if (adev->gmc.translate_further) { in mmhub_v4_1_0_init_cache_regs()
H A Dmmhub_v2_0.c193 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v2_0_init_gart_aperture_regs()
195 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v2_0_init_gart_aperture_regs()
198 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v2_0_init_gart_aperture_regs()
200 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v2_0_init_gart_aperture_regs()
211 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_0_init_system_aperture_regs()
212 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_0_init_system_aperture_regs()
216 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v2_0_init_system_aperture_regs()
218 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v2_0_init_system_aperture_regs()
289 if (adev->gmc.translate_further) { in mmhub_v2_0_init_cache_regs()
380 !adev->gmc.noretry); in mmhub_v2_0_setup_vmid_config()
H A Damdgpu_amdkfd.c229 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; in amdgpu_amdkfd_device_init()
240 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; in amdgpu_amdkfd_device_fini_sw()
488 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) in amdgpu_amdkfd_get_local_mem_info()
498 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; in amdgpu_amdkfd_get_local_mem_info()
499 mem_info->local_mem_size_private = adev->gmc.real_vram_size - in amdgpu_amdkfd_get_local_mem_info()
500 adev->gmc.visible_vram_size; in amdgpu_amdkfd_get_local_mem_info()
502 mem_info->vram_width = adev->gmc.vram_width; in amdgpu_amdkfd_get_local_mem_info()
505 &adev->gmc.aper_base, in amdgpu_amdkfd_get_local_mem_info()
794 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { in amdgpu_amdkfd_xcp_memory_size()
795 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) { in amdgpu_amdkfd_xcp_memory_size()
[all …]
H A Dmmhub_v3_0_1.c157 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_0_1_init_gart_aperture_regs()
159 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_0_1_init_gart_aperture_regs()
162 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_0_1_init_gart_aperture_regs()
164 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_0_1_init_gart_aperture_regs()
174 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_1_init_system_aperture_regs()
175 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_1_init_system_aperture_regs()
184 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_0_1_init_system_aperture_regs()
186 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_0_1_init_system_aperture_regs()
251 if (adev->gmc.translate_further) { in mmhub_v3_0_1_init_cache_regs()
H A Dmmhub_v3_0.c149 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_0_init_gart_aperture_regs()
151 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_0_init_gart_aperture_regs()
154 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_0_init_gart_aperture_regs()
156 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_0_init_gart_aperture_regs()
174 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_init_system_aperture_regs()
175 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_init_system_aperture_regs()
179 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_0_init_system_aperture_regs()
181 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_0_init_system_aperture_regs()
252 if (adev->gmc.translate_further) { in mmhub_v3_0_init_cache_regs()
H A Dumc_v8_10.h37 (adev)->gmc.num_umc - hweight32((adev)->gmc.m_half_use) * 2)
H A Damdgpu_device.c649 if (!adev->gmc.noretry && !amdgpu_passthrough(adev)) in amdgpu_device_detect_runtime_pm_mode()
763 last = min(pos + size, adev->gmc.visible_vram_size); in amdgpu_device_aper_access()
1117 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size); in amdgpu_device_resize_fb_bar()
1148 if (adev->gmc.real_vram_size && in amdgpu_device_resize_fb_bar()
1149 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) in amdgpu_device_resize_fb_bar()
2102 if (adev->gmc.xgmi.supported) in amdgpu_device_ip_early_init()
2434 if (adev->gmc.xgmi.num_physical_nodes > 1) { in amdgpu_device_ip_init()
2709 ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) || in amdgpu_device_ip_late_init()
2713 if (adev->gmc.xgmi.num_physical_nodes > 1) { in amdgpu_device_ip_late_init()
2729 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) { in amdgpu_device_ip_late_init()
[all …]
H A Dhdp_v4_0.c156 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in hdp_v4_0_init_registers()
157 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); in hdp_v4_0_init_registers()
H A Damdgpu_vm_pt.c416 flags = AMDGPU_PTE_EXECUTABLE | adev->gmc.init_pte_flags; in amdgpu_vm_pt_clear()
453 if (!adev->gmc.is_app_apu) in amdgpu_vm_pt_create()
670 *flags |= adev->gmc.noretry_flags; in amdgpu_vm_pte_update_noretry_flags()
700 flags |= AMDGPU_PTE_EXECUTABLE | adev->gmc.init_pte_flags; in amdgpu_vm_pte_update_flags()
718 adev->gmc.gmc_funcs->override_vm_pte_flags && in amdgpu_vm_pte_update_flags()
H A Dumc_v8_14.h36 (UMC_V8_14_CHANNEL_INSTANCE_NUM * (adev)->gmc.num_umc)
H A Dimu_v11_0_3.c126 data = adev->gmc.vram_start >> 24; in program_rlc_ram_register_setting()
128 data = adev->gmc.vram_end >> 24; in program_rlc_ram_register_setting()
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c82 unsigned int *gmc, in loongson_gfxpll_get_rates() argument
110 if (gmc) in loongson_gfxpll_get_rates()
111 *gmc = gmc_mhz; in loongson_gfxpll_get_rates()
122 unsigned int dc, gmc, gpu; in loongson_gfxpll_print() local
134 this->funcs->get_rates(this, &dc, &gmc, &gpu); in loongson_gfxpll_print()
136 drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu); in loongson_gfxpll_print()

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