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Searched refs:gmc (Results 1 – 25 of 80) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gmc.c45 return adev->gmc.xgmi.connected_to_cpu || amdgpu_virt_xgmi_migrate_enabled(adev); in amdgpu_gmc_is_pdb0_enabled()
60 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; in amdgpu_gmc_pdb0_alloc()
61 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; in amdgpu_gmc_pdb0_alloc()
74 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
78 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); in amdgpu_gmc_pdb0_alloc()
82 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_gmc_pdb0_alloc()
85 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); in amdgpu_gmc_pdb0_alloc()
89 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
93 amdgpu_bo_unpin(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
95 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
[all …]
H A Dgmc_v9_0.c724 adev->gmc.vm_fault.num_types = 1; in gmc_v9_0_set_irq_funcs()
725 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; in gmc_v9_0_set_irq_funcs()
728 !adev->gmc.xgmi.connected_to_cpu && in gmc_v9_0_set_irq_funcs()
729 !adev->gmc.is_app_apu) { in gmc_v9_0_set_irq_funcs()
730 adev->gmc.ecc_irq.num_types = 1; in gmc_v9_0_set_irq_funcs()
731 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; in gmc_v9_0_set_irq_funcs()
839 spin_lock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
901 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
1054 if (!adev->gmc.translate_further) in gmc_v9_0_get_vm_pde()
1108 adev->gmc.xgmi.connected_to_cpu) in gmc_v9_0_get_coherence_flags()
[all …]
H A Dgmc_v7_0.c160 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v7_0_init_microcode()
164 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v7_0_init_microcode()
185 if (!adev->gmc.fw) in gmc_v7_0_mc_load_microcode()
188 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v7_0_mc_load_microcode()
191 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v7_0_mc_load_microcode()
194 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
197 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
294 adev->gmc.vram_start >> 12); in gmc_v7_0_mc_program()
296 adev->gmc.vram_end >> 12); in gmc_v7_0_mc_program()
300 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); in gmc_v7_0_mc_program()
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H A Dgmc_v8_0.c262 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v8_0_init_microcode()
266 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v8_0_init_microcode()
295 if (!adev->gmc.fw) in gmc_v8_0_tonga_mc_load_microcode()
298 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_tonga_mc_load_microcode()
301 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_tonga_mc_load_microcode()
304 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
307 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
364 if (!adev->gmc.fw) in gmc_v8_0_polaris_mc_load_microcode()
367 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_polaris_mc_load_microcode()
370 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_polaris_mc_load_microcode()
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H A Damdgpu_xgmi.c299 if (adev->gmc.xgmi.num_physical_nodes <= 1) in amdgpu_xgmi_get_ext_link()
350 if (adev->gmc.xgmi.num_physical_nodes <= 1) in amdgpu_get_xgmi_link_status()
450 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); in amdgpu_xgmi_show_device_id()
461 return sysfs_emit(buf, "%u\n", adev->gmc.xgmi.physical_node_id); in amdgpu_xgmi_show_physical_id()
510 if (top->nodes[i].node_id == adev->gmc.xgmi.node_id) { in amdgpu_xgmi_show_connected_port_num()
678 if (!adev->gmc.xgmi.hive_id) in amdgpu_get_xgmi_hive()
689 if (hive->hive_id == adev->gmc.xgmi.hive_id) in amdgpu_get_xgmi_hive()
741 hive->hive_id = adev->gmc.xgmi.hive_id; in amdgpu_get_xgmi_hive()
813 request_adev->gmc.xgmi.node_id, in amdgpu_xgmi_set_pstate()
814 request_adev->gmc.xgmi.hive_id, ret); in amdgpu_xgmi_set_pstate()
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H A Dgfxhub_v1_1.c88 if (max_region || adev->gmc.xgmi.connected_to_cpu) { in gfxhub_v1_1_get_xgmi_info()
89 adev->gmc.xgmi.num_physical_nodes = max_region + 1; in gfxhub_v1_1_get_xgmi_info()
91 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) in gfxhub_v1_1_get_xgmi_info()
95 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
99 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
104 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) in gfxhub_v1_1_get_xgmi_info()
107 adev->gmc.xgmi.node_segment_size = seg_size; in gfxhub_v1_1_get_xgmi_info()
H A Dmmhub_v4_2_0.c137 if (adev->gmc.pdb0_bo) in mmhub_v4_2_0_mid_init_gart_aperture_regs()
138 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in mmhub_v4_2_0_mid_init_gart_aperture_regs()
145 if (adev->gmc.pdb0_bo) { in mmhub_v4_2_0_mid_init_gart_aperture_regs()
148 (u32)(adev->gmc.fb_start >> 12)); in mmhub_v4_2_0_mid_init_gart_aperture_regs()
151 (u32)(adev->gmc.fb_start >> 44)); in mmhub_v4_2_0_mid_init_gart_aperture_regs()
155 (u32)(adev->gmc.fb_end >> 12)); in mmhub_v4_2_0_mid_init_gart_aperture_regs()
158 (u32)(adev->gmc.fb_end >> 44)); in mmhub_v4_2_0_mid_init_gart_aperture_regs()
162 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v4_2_0_mid_init_gart_aperture_regs()
165 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v4_2_0_mid_init_gart_aperture_regs()
169 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v4_2_0_mid_init_gart_aperture_regs()
[all …]
H A Dmmhub_v1_0.c48 adev->gmc.fb_start = base; in mmhub_v1_0_get_fb_location()
49 adev->gmc.fb_end = top; in mmhub_v1_0_get_fb_location()
75 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
77 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
80 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
82 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v1_0_init_system_aperture_regs()
93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v1_0_init_system_aperture_regs()
97 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v1_0_init_system_aperture_regs()
109 max((adev->gmc.fb_end >> 18) + 0x1, in mmhub_v1_0_init_system_aperture_regs()
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H A Damdgpu_gmc.h366 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((…
367 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping(…
368 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (l…
370 ((adev)->gmc.gmc_funcs->get_vm_pte((adev), (vm), (bo), (vm_flags), \
373 (adev)->gmc.gmc_funcs->override_vm_pte_flags \
375 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
378 _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \
389 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) in amdgpu_gmc_vram_full_visible() argument
391 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); in amdgpu_gmc_vram_full_visible()
393 return (gmc->real_vram_size == gmc->visible_vram_size); in amdgpu_gmc_vram_full_visible()
H A Dgfxhub_v12_0.c148 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v12_0_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v12_0_init_gart_aperture_regs()
153 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v12_0_init_gart_aperture_regs()
155 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v12_0_init_gart_aperture_regs()
164 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v12_0_init_system_aperture_regs()
165 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v12_0_init_system_aperture_regs()
169 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v12_0_init_system_aperture_regs()
171 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v12_0_init_system_aperture_regs()
174 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start in gfxhub_v12_0_init_system_aperture_regs()
242 if (adev->gmc.translate_further) { in gfxhub_v12_0_init_cache_regs()
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H A Dgfxhub_v11_5_0.c145 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v11_5_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v11_5_0_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v11_5_0_init_gart_aperture_regs()
152 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v11_5_0_init_gart_aperture_regs()
160 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v11_5_0_init_system_aperture_regs()
161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v11_5_0_init_system_aperture_regs()
165 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v11_5_0_init_system_aperture_regs()
168 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v11_5_0_init_system_aperture_regs()
237 if (adev->gmc.translate_further) { in gfxhub_v11_5_0_init_cache_regs()
364 adev->gmc.vram_start >> 24); in gfxhub_v11_5_0_gart_enable()
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H A Dgfxhub_v3_0.c140 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
142 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
156 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_init_system_aperture_regs()
157 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_init_system_aperture_regs()
162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v3_0_init_system_aperture_regs()
164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v3_0_init_system_aperture_regs()
234 if (adev->gmc.translate_further) { in gfxhub_v3_0_init_cache_regs()
361 adev->gmc.vram_start >> 24); in gfxhub_v3_0_gart_enable()
[all …]
H A Dgfxhub_v2_0.c141 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
143 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
146 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
148 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_0_init_system_aperture_regs()
159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_0_init_system_aperture_regs()
163 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
165 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
233 if (adev->gmc.translate_further) { in gfxhub_v2_0_init_cache_regs()
314 !adev->gmc.noretry); in gfxhub_v2_0_setup_vmid_config()
H A Dmmhub_v2_3.c140 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
142 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
157 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_3_init_system_aperture_regs()
158 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_3_init_system_aperture_regs()
162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v2_3_init_system_aperture_regs()
164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v2_3_init_system_aperture_regs()
228 if (adev->gmc.translate_further) { in mmhub_v2_3_init_cache_regs()
313 !adev->gmc.noretry); in mmhub_v2_3_setup_vmid_config()
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H A Damdgpu_ttm.c135 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && in amdgpu_evict_flags()
147 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; in amdgpu_evict_flags()
231 *addr = adev->gmc.gart_start; in amdgpu_ttm_map_buffer()
466 if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size) in amdgpu_res_cpu_visible()
633 mem->bus.offset += adev->gmc.aper_base; in amdgpu_ttm_io_mem_reserve()
668 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; in amdgpu_ttm_io_mem_pfn()
684 return adev->gmc.gart_start; in amdgpu_ttm_domain_start()
686 return adev->gmc.vram_start; in amdgpu_ttm_domain_start()
994 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; in amdgpu_ttm_alloc_gart()
1180 if (adev->gmc.mem_partitions && abo->xcp_id >= 0) in amdgpu_ttm_tt_create()
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H A Dgfxhub_v3_0_3.c143 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v3_0_3_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v3_0_3_init_gart_aperture_regs()
148 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v3_0_3_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v3_0_3_init_gart_aperture_regs()
162 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_3_init_system_aperture_regs()
163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_3_init_system_aperture_regs()
167 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v3_0_3_init_system_aperture_regs()
169 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v3_0_3_init_system_aperture_regs()
239 if (adev->gmc.translate_further) { in gfxhub_v3_0_3_init_cache_regs()
H A Damdgpu_vram_mgr.c107 return sysfs_emit(buf, "%llu\n", adev->gmc.real_vram_size); in amdgpu_mem_info_vram_total_show()
124 return sysfs_emit(buf, "%llu\n", adev->gmc.visible_vram_size); in amdgpu_mem_info_vis_vram_total_show()
180 switch (adev->gmc.vram_vendor) { in amdgpu_mem_info_vram_vendor()
234 !adev->gmc.vram_vendor) in amdgpu_vram_attrs_is_visible()
262 if (start >= adev->gmc.visible_vram_size) in amdgpu_vram_mgr_vis_size()
265 return (end > adev->gmc.visible_vram_size ? in amdgpu_vram_mgr_vis_size()
266 adev->gmc.visible_vram_size : end) - start; in amdgpu_vram_mgr_vis_size()
285 if (amdgpu_gmc_vram_full_visible(&adev->gmc)) in amdgpu_vram_mgr_bo_visible_size()
288 if (res->start >= adev->gmc.visible_vram_size >> PAGE_SHIFT) in amdgpu_vram_mgr_bo_visible_size()
464 max_bytes = adev->gmc.mc_vram_size; in amdgpu_vram_mgr_new()
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H A Dmmhub_v3_0_2.c150 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_0_2_init_gart_aperture_regs()
152 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_0_2_init_gart_aperture_regs()
155 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_0_2_init_gart_aperture_regs()
157 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_0_2_init_gart_aperture_regs()
167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
168 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
178 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_0_2_init_system_aperture_regs()
180 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_0_2_init_system_aperture_regs()
252 if (adev->gmc.translate_further) { in mmhub_v3_0_2_init_cache_regs()
H A Dmmhub_v2_0.c208 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v2_0_init_gart_aperture_regs()
210 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v2_0_init_gart_aperture_regs()
213 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v2_0_init_gart_aperture_regs()
215 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v2_0_init_gart_aperture_regs()
226 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_0_init_system_aperture_regs()
227 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_0_init_system_aperture_regs()
231 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v2_0_init_system_aperture_regs()
233 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v2_0_init_system_aperture_regs()
304 if (adev->gmc.translate_further) { in mmhub_v2_0_init_cache_regs()
395 !adev->gmc.noretry); in mmhub_v2_0_setup_vmid_config()
H A Dmmhub_v4_1_0.c149 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v4_1_0_init_gart_aperture_regs()
151 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v4_1_0_init_gart_aperture_regs()
154 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v4_1_0_init_gart_aperture_regs()
156 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v4_1_0_init_gart_aperture_regs()
174 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v4_1_0_init_system_aperture_regs()
175 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v4_1_0_init_system_aperture_regs()
179 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v4_1_0_init_system_aperture_regs()
181 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v4_1_0_init_system_aperture_regs()
184 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start + in mmhub_v4_1_0_init_system_aperture_regs()
253 if (adev->gmc.translate_further) { in mmhub_v4_1_0_init_cache_regs()
H A Damdgpu_amdkfd.c229 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; in amdgpu_amdkfd_device_init()
240 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; in amdgpu_amdkfd_device_fini_sw()
488 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) in amdgpu_amdkfd_get_local_mem_info()
498 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; in amdgpu_amdkfd_get_local_mem_info()
499 mem_info->local_mem_size_private = adev->gmc.real_vram_size - in amdgpu_amdkfd_get_local_mem_info()
500 adev->gmc.visible_vram_size; in amdgpu_amdkfd_get_local_mem_info()
502 mem_info->vram_width = adev->gmc.vram_width; in amdgpu_amdkfd_get_local_mem_info()
505 &adev->gmc.aper_base, in amdgpu_amdkfd_get_local_mem_info()
794 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { in amdgpu_amdkfd_xcp_memory_size()
795 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) { in amdgpu_amdkfd_xcp_memory_size()
[all …]
H A Dmmhub_v3_0_1.c166 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_0_1_init_gart_aperture_regs()
168 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_0_1_init_gart_aperture_regs()
171 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_0_1_init_gart_aperture_regs()
173 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_0_1_init_gart_aperture_regs()
183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_1_init_system_aperture_regs()
184 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_1_init_system_aperture_regs()
193 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_0_1_init_system_aperture_regs()
195 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_0_1_init_system_aperture_regs()
260 if (adev->gmc.translate_further) { in mmhub_v3_0_1_init_cache_regs()
H A Dmmhub_v3_0.c157 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_0_init_gart_aperture_regs()
159 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_0_init_gart_aperture_regs()
162 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_0_init_gart_aperture_regs()
164 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_0_init_gart_aperture_regs()
182 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_init_system_aperture_regs()
183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_init_system_aperture_regs()
187 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_0_init_system_aperture_regs()
189 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_0_init_system_aperture_regs()
260 if (adev->gmc.translate_further) { in mmhub_v3_0_init_cache_regs()
H A Dumc_v8_10.h37 (adev)->gmc.num_umc - hweight32((adev)->gmc.m_half_use) * 2)
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c82 unsigned int *gmc, in loongson_gfxpll_get_rates() argument
110 if (gmc) in loongson_gfxpll_get_rates()
111 *gmc = gmc_mhz; in loongson_gfxpll_get_rates()
122 unsigned int dc, gmc, gpu; in loongson_gfxpll_print() local
134 this->funcs->get_rates(this, &dc, &gmc, &gpu); in loongson_gfxpll_print()
136 drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu); in loongson_gfxpll_print()

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