Searched refs:gimr (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/irqchip/ |
| H A D | irq-realtek-rtl.c | 56 u32 gimr; in enable_gimr() local
58 gimr = readl_be(REG(cpu, RTL_ICTL_GIMR)); in enable_gimr()
59 gimr |= BIT(hw_irq); in enable_gimr()
60 writel_be(gimr, REG(cpu, RTL_ICTL_GIMR)); in enable_gimr()
65 u32 gimr; in disable_gimr() local
67 gimr = readl_be(REG(cpu, RTL_ICTL_GIMR)); in disable_gimr()
68 gimr &= ~BIT(hw_irq); in disable_gimr()
69 writel_be(gimr, REG(cpu, RTL_ICTL_GIMR)); in disable_gimr()
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| /linux/drivers/gpio/ |
| H A D | gpio-tangier.c | 59 u32 gimr; member
215 void __iomem *gimr; in tng_irq_unmask_mask() local
219 gimr = gpio_reg_and_bit(&priv->chip, gpio, GIMR, &shift); in tng_irq_unmask_mask()
223 value = readl(gimr); in tng_irq_unmask_mask()
228 writel(value, gimr); in tng_irq_unmask_mask()
357 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); in tng_irq_handler() local
361 enabled = readl(gimr); in tng_irq_handler()
481 ctx->gimr = readl(gpio_reg(&priv->chip, base, GIMR)); in tng_gpio_suspend()
504 writel(ctx->gimr, gpio_reg(&priv->chip, base, GIMR)); in tng_gpio_resume()
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