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Searched refs:gicv5_wait_for_op_atomic (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/irqchip/
H A Dirq-gic-v5-irs.c59 return gicv5_wait_for_op_atomic(irs_data->irs_base, GICV5_IRS_IST_STATUSR, in gicv5_irs_ist_synchronise()
409 ret = gicv5_wait_for_op_atomic(irs_data->irs_base, GICV5_IRS_SPI_STATUSR, in gicv5_irs_wait_for_spi_op()
424 ret = gicv5_wait_for_op_atomic(irs_data->irs_base, GICV5_IRS_PE_STATUSR, in gicv5_irs_wait_for_irs_pe()
486 return gicv5_wait_for_op_atomic(irs_data->irs_base, GICV5_IRS_CR0, in gicv5_irs_wait_for_idle()
H A Dirq-gic-v5-iwb.c35 return gicv5_wait_for_op_atomic(iwb_node->iwb_base, GICV5_IWB_WENABLE_STATUSR, in gicv5_iwb_wait_for_wenabler()
H A Dirq-gic-v5-its.c85 return gicv5_wait_for_op_atomic(its->its_base, GICV5_ITS_STATUSR, in gicv5_its_cache_sync()
1054 return gicv5_wait_for_op_atomic(its->its_base, GICV5_ITS_CR0, in gicv5_its_write_cr0()
/linux/include/linux/irqchip/
H A Darm-gic-v5.h337 #define gicv5_wait_for_op_atomic(base, reg, mask, val) \ macro