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Searched refs:gic (Results 1 – 25 of 351) sorted by relevance

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/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-aemv8a.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
101 gic: interrupt-controller@2c001000 { label
102 compatible = "arm,gic-400", "arm,cortex-a15-gic";
141 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
146 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfoundation-v8.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
138 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
139 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
140 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfvp-base-revc.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
222 gic: interrupt-controller@2f000000 { label
223 compatible = "arm,gic-v3";
238 compatible = "arm,gic-v3-its";
338 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
339 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
340 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
341 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Djuno-base.dtsi69 gic: interrupt-controller@2c010000 { label
70 compatible = "arm,gic-400", "arm,cortex-a15-gic";
83 compatible = "arm,gic-v2m-frame";
89 compatible = "arm,gic-v2m-frame";
95 compatible = "arm,gic-v2m-frame";
101 compatible = "arm,gic-v2m-frame";
703 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
704 <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
705 <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
706 <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
[all …]
H A Dmorello.dtsi6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
149 interrupt-parent = <&gic>;
214 interrupt-parent = <&gic>;
227 gic: interrupt-controller@30000000 { label
228 compatible = "arm,gic-v3";
242 compatible = "arm,gic-v3-its";
250 compatible = "arm,gic-v3-its";
258 compatible = "arm,gic-v3-its";
266 compatible = "arm,gic-v3-its";
/linux/drivers/irqchip/
H A Dirq-gic.c337 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
338 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
370 generic_handle_domain_irq(gic->domain, irqnr); in gic_handle_irq()
400 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); in gic_irq_print_chip() local
402 if (gic->domain->pm_dev) in gic_irq_print_chip()
403 seq_puts(p, gic->domain->pm_dev->of_node->name); in gic_irq_print_chip()
405 seq_printf(p, "GIC-%d", (int)(gic - &gic_data[0])); in gic_irq_print_chip()
415 static u8 gic_get_cpumask(struct gic_chip_data *gic) in gic_get_cpumask() argument
417 void __iomem *base = gic_data_dist_base(gic); in gic_get_cpumask()
440 static void gic_cpu_if_up(struct gic_chip_data *gic) in gic_cpu_if_up() argument
[all …]
H A Dirq-gic-pm.c28 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_resume() local
42 if (!gic) in gic_runtime_resume()
45 gic_dist_restore(gic); in gic_runtime_resume()
46 gic_cpu_restore(gic); in gic_runtime_resume()
54 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_suspend() local
57 gic_dist_save(gic); in gic_runtime_suspend()
58 gic_cpu_save(gic); in gic_runtime_suspend()
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-ns.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
75 gic: interrupt-controller@21000 { label
76 compatible = "arm,cortex-a9-gic";
106 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
109 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
110 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
111 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
112 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
113 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dbcm53573.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
40 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dvexpress-v2p-ca5s.dts19 interrupt-parent = <&gic>;
121 gic: interrupt-controller@2c001000 { label
122 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
221 interrupt-map = <0 0 &gic 0 36 4>,
222 <0 1 &gic 0 37 4>,
223 <0 2 &gic 0 38 4>,
224 <0 3 &gic 0 39 4>;
/linux/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/linux/drivers/net/ethernet/microsoft/mana/
H A Dgdma_main.c714 struct gdma_irq_context *gic; in mana_gd_register_irq() local
734 gic = xa_load(&gc->irq_contexts, msi_index); in mana_gd_register_irq()
735 if (WARN_ON(!gic)) in mana_gd_register_irq()
738 spin_lock_irqsave(&gic->lock, flags); in mana_gd_register_irq()
739 list_add_rcu(&queue->entry, &gic->eq_list); in mana_gd_register_irq()
740 spin_unlock_irqrestore(&gic->lock, flags); in mana_gd_register_irq()
748 struct gdma_irq_context *gic; in mana_gd_deregister_irq() local
761 gic = xa_load(&gc->irq_contexts, msix_index); in mana_gd_deregister_irq()
762 if (WARN_ON(!gic)) in mana_gd_deregister_irq()
765 spin_lock_irqsave(&gic->lock, flags); in mana_gd_deregister_irq()
[all …]
/linux/tools/testing/selftests/kvm/arm64/
H A Dvgic_init.c824 static void test_sysreg_array(int gic, const struct sr_def *sr, int nr, in test_sysreg_array() argument
844 ret = __kvm_has_device_attr(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, in test_sysreg_array()
849 ret = __kvm_device_attr_get(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, in test_sysreg_array()
851 TEST_ASSERT(ret == 0 || !check(gic, &sr[i], "read"), "%s unreadable", sr[i].name); in test_sysreg_array()
852 ret = __kvm_device_attr_set(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, in test_sysreg_array()
854 TEST_ASSERT(ret == 0 || !check(gic, &sr[i], "write"), "%s unwritable", sr[i].name); in test_sysreg_array()
858 static u8 get_ctlr_pribits(int gic) in get_ctlr_pribits() argument
864 ret = __kvm_device_attr_get(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, in get_ctlr_pribits()
874 static int check_unaccessible_el1_regs(int gic, const struct sr_def *sr, const char *what) in check_unaccessible_el1_regs() argument
879 if (get_ctlr_pribits(gic) > in check_unaccessible_el1_regs()
897 get_vtr_pribits(int gic) get_vtr_pribits() argument
913 check_unaccessible_el2_regs(int gic,const struct sr_def * sr,const char * what) check_unaccessible_el2_regs() argument
942 int gic; test_v3_sysregs() local
[all...]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi30 interrupt-parent = <&gic>;
84 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
85 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
86 <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
87 <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
88 <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
89 <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
90 <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
91 <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/arm64/boot/dts/freescale/
H A Ds32v234.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
91 gic: interrupt-controller@7d001000 { label
92 compatible = "arm,cortex-a15-gic";
108 interrupt-parent = <&gic>;
115 interrupt-parent = <&gic>;
131 interrupt-parent = <&gic>;
H A Dfsl-ls1043a.dtsi13 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
290 gic: interrupt-controller@1400000 { label
291 compatible = "arm,gic-400";
332 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
333 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
334 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
335 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
336 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
337 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/arch/mips/boot/dts/img/
H A Dboston.dts7 #include <dt-bindings/interrupt-controller/mips-gic.h>
48 interrupt-parent = <&gic>;
78 interrupt-parent = <&gic>;
108 interrupt-parent = <&gic>;
181 gic: interrupt-controller@16120000 { label
182 compatible = "mti,gic";
189 compatible = "mti,gic-timer";
227 interrupt-parent = <&gic>;
/linux/arch/mips/include/asm/
H A Dmips-gic.h8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
32 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
36 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
37 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
41 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
42 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
46 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
47 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
/linux/arch/mips/boot/dts/mti/
H A Dmalta.dts5 #include <dt-bindings/interrupt-controller/mips-gic.h>
23 gic: interrupt-controller@1bdc0000 { label
24 compatible = "mti,gic";
31 * Declare the interrupt-parent even though the mti,gic
39 compatible = "mti,gic-timer";
50 interrupt-parent = <&gic>;
H A Dsead3.dts8 #include <dt-bindings/interrupt-controller/mips-gic.h>
43 gic: interrupt-controller@1b1c0000 { label
44 compatible = "mti,gic";
51 * Declare the interrupt-parent even though the mti,gic
63 interrupt-parent = <&gic>;
226 interrupt-parent = <&gic>;
241 interrupt-parent = <&gic>;
252 interrupt-parent = <&gic>;
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0.dtsi8 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
46 interrupt-parent = <&gic>;
48 gic: interrupt-controller@3000000 { label
49 compatible = "arm,gic-v3";
64 compatible = "arm,gic-v3-its";
/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021-achip.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
48 gic: interrupt-controller@9f101000 { label
49 compatible = "arm,cortex-a7-gic";
79 interrupt-parent = <&gic>;
/linux/include/linux/irqchip/
H A Darm-gic.h143 void gic_cpu_save(struct gic_chip_data *gic);
144 void gic_cpu_restore(struct gic_chip_data *gic);
145 void gic_dist_save(struct gic_chip_data *gic);
146 void gic_dist_restore(struct gic_chip_data *gic);
158 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq);
/linux/arch/arm64/boot/dts/bst/
H A Dbstc1200.dtsi2 #include <dt-bindings/interrupt-controller/arm-gic.h>
63 interrupt-parent = <&gic>;
75 gic: interrupt-controller@32800000 { label
76 compatible = "arm,gic-v3";
91 interrupt-parent = <&gic>;

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