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Searched refs:gart (Results 1 – 25 of 28) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gart.c120 unsigned int order = get_order(adev->gart.table_size); in amdgpu_gart_table_ram_alloc()
130 if (adev->gart.bo != NULL) in amdgpu_gart_table_ram_alloc()
145 dma_addr = dma_map_page(&adev->pdev->dev, p, 0, adev->gart.table_size, in amdgpu_gart_table_ram_alloc()
166 sg->sgl->length = adev->gart.table_size; in amdgpu_gart_table_ram_alloc()
168 sg->sgl->dma_length = adev->gart.table_size; in amdgpu_gart_table_ram_alloc()
172 bp.size = adev->gart.table_size; in amdgpu_gart_table_ram_alloc()
199 adev->gart.bo = bo; in amdgpu_gart_table_ram_alloc()
200 adev->gart.ptr = page_to_virt(p); in amdgpu_gart_table_ram_alloc()
202 ret = amdgpu_ttm_alloc_gart(&adev->gart.bo->tbo); in amdgpu_gart_table_ram_alloc()
231 unsigned int order = get_order(adev->gart.table_size); in amdgpu_gart_table_ram_free()
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H A Dgmc_v11_0.c723 if (adev->gart.bo) { in gmc_v11_0_gart_init()
733 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v11_0_gart_init()
734 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | in gmc_v11_0_gart_init()
908 if (adev->gart.bo == NULL) { in gmc_v11_0_gart_enable()
929 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); in gmc_v11_0_gart_enable()
H A Dmmhub_v1_0.c70 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v1_0_init_gart_aperture_regs()
234 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v1_0_init_saw()
H A Damdgpu_gmc.c759 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); in amdgpu_gmc_flush_gpu_tlb()
1143 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW? in amdgpu_gmc_init_pdb0()
1149 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo); in amdgpu_gmc_init_pdb0()
H A Dgfxhub_v2_0.c136 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v2_0_init_gart_aperture_regs()
H A Dgfxhub_v1_0.c61 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v1_0_init_gart_aperture_regs()
H A Dmmhub_v2_0.c188 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v2_0_init_gart_aperture_regs()
H A Dmmhub_v2_3.c126 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v2_3_init_gart_aperture_regs()
H A Dvce_v1_0.c576 num_pages, flags, adev->gart.ptr); in vce_v1_0_ensure_vcpu_bo_32bit_addr()
H A Dgfxhub_v2_1.c139 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v2_1_init_gart_aperture_regs()
H A Dgfxhub_v1_2.c85 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
H A Damdgpu_ttm.c263 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); in amdgpu_ttm_map_buffer()
1477 flags |= adev->gart.gart_pte_flags; in amdgpu_ttm_tt_pte_flags()
2490 adev->gart.bo); in amdgpu_ttm_prepare_job()
H A Dgfxhub_v12_1.c102 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v12_1_xcc_init_gart_aperture_regs()
/linux/drivers/gpu/drm/radeon/
H A Drs400.c85 if (rdev->gart.ptr) { in rs400_gart_init()
107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rs400_gart_init()
165 tmp = (u32)rdev->gart.table_addr & 0xfffff000; in rs400_gart_enable()
166 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; in rs400_gart_enable()
193 (unsigned long long)rdev->gart.table_addr); in rs400_gart_enable()
194 rdev->gart.ready = true; in rs400_gart_enable()
237 u32 *gtt = rdev->gart.ptr; in rs400_gart_set_page()
H A Dradeon_asic.c166 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in radeon_agp_disable()
167 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in radeon_agp_disable()
168 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in radeon_agp_disable()
172 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in radeon_agp_disable()
173 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in radeon_agp_disable()
174 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in radeon_agp_disable()
208 .gart = {
276 .gart = {
372 .gart = {
440 .gart = {
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H A Dr300.c122 void __iomem *ptr = rdev->gart.ptr; in rv370_pcie_gart_set_page()
134 if (rdev->gart.robj) { in rv370_pcie_gart_init()
144 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rv370_pcie_gart_init()
145 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in rv370_pcie_gart_init()
146 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in rv370_pcie_gart_init()
147 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in rv370_pcie_gart_init()
157 if (rdev->gart.robj == NULL) { in rv370_pcie_gart_enable()
172 table_addr = rdev->gart.table_addr; in rv370_pcie_gart_enable()
187 rdev->gart.ready = true; in rv370_pcie_gart_enable()
H A Drs600.c549 if (rdev->gart.robj) { in rs600_gart_init()
558 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
567 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
604 rdev->gart.table_addr); in rs600_gart_enable()
621 (unsigned long long)rdev->gart.table_addr); in rs600_gart_enable()
622 rdev->gart.ready = true; in rs600_gart_enable()
662 void __iomem *ptr = (void *)rdev->gart.ptr; in rs600_gart_set_page()
H A Drv770.c899 if (rdev->gart.robj == NULL) { in rv770_pcie_gart_enable()
928 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in rv770_pcie_gart_enable()
939 (unsigned long long)rdev->gart.table_addr); in rv770_pcie_gart_enable()
940 rdev->gart.ready = true; in rv770_pcie_gart_enable()
H A Dr100.c656 if (rdev->gart.ptr) { in r100_pci_gart_init()
664 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in r100_pci_gart_init()
665 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in r100_pci_gart_init()
666 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in r100_pci_gart_init()
667 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in r100_pci_gart_init()
682 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); in r100_pci_gart_enable()
688 (unsigned long long)rdev->gart.table_addr); in r100_pci_gart_enable()
689 rdev->gart.ready = true; in r100_pci_gart_enable()
712 u32 *gtt = rdev->gart.ptr; in r100_pci_gart_set_page()
H A Dradeon_ttm.c857 if (p >= rdev->gart.num_cpu_pages) in radeon_ttm_gtt_read()
860 page = rdev->gart.pages[p]; in radeon_ttm_gtt_read()
H A Dni.c1252 if (rdev->gart.robj == NULL) { in cayman_pcie_gart_enable()
1281 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cayman_pcie_gart_enable()
1327 (unsigned long long)rdev->gart.table_addr); in cayman_pcie_gart_enable()
1328 rdev->gart.ready = true; in cayman_pcie_gart_enable()
H A Dradeon_vm.c366 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8; in radeon_vm_set_pages()
598 result = rdev->gart.pages_entry[addr >> RADEON_GPU_PAGE_SHIFT]; in radeon_vm_map_gart()
H A Dr600.c1082 void __iomem *ptr = (void *)rdev->gart.ptr; in r600_pcie_gart_tlb_flush()
1116 if (rdev->gart.robj) { in r600_pcie_gart_init()
1124 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in r600_pcie_gart_init()
1133 if (rdev->gart.robj == NULL) { in r600_pcie_gart_enable()
1170 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in r600_pcie_gart_enable()
1181 (unsigned long long)rdev->gart.table_addr); in r600_pcie_gart_enable()
1182 rdev->gart.ready = true; in r600_pcie_gart_enable()
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_chan.c109 nvif_object_dtor(&chan->gart); in nouveau_channel_del()
361 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) in nouveau_channel_init() argument
432 ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart, in nouveau_channel_init()
434 &chan->gart); in nouveau_channel_init()
502 bool priv, u64 runm, u32 vram, u32 gart, struct nouveau_channel **pchan) in nouveau_channel_new() argument
512 ret = nouveau_channel_init(*pchan, vram, gart); in nouveau_channel_new()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_migrate.c79 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); in svm_migrate_gart_map()
91 pte_flags |= adev->gart.gart_pte_flags; in svm_migrate_gart_map()

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