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Searched refs:fixed_cntr_mask (Results 1 – 2 of 2) sorted by relevance

/linux/arch/x86/events/
H A Dcore.c258 unsigned long *fixed_cntr_mask) in check_hw_exists() argument
283 if (*(u64 *)fixed_cntr_mask) { in check_hw_exists()
288 for_each_set_bit(i, fixed_cntr_mask, X86_PMC_IDX_MAX) { in check_hw_exists()
1525 unsigned long *cntr_mask, *fixed_cntr_mask; in perf_event_print_debug() local
1536 fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); in perf_event_print_debug()
1577 for_each_set_bit(idx, fixed_cntr_mask, X86_PMC_IDX_MAX) { in perf_event_print_debug()
2090 if (!check_hw_exists(&pmu, x86_pmu.cntr_mask, x86_pmu.fixed_cntr_mask)) in init_hw_perf_events()
2485 if (!test_bit(i - INTEL_PMC_IDX_FIXED, hybrid(cpuc->pmu, fixed_cntr_mask))) in perf_clear_dirty_counters()
/linux/arch/x86/events/intel/
H A Dcore.c2945 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); in intel_pmu_reset() local
2960 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) { in intel_pmu_reset()
4945 u64 *fixed_cntr_mask, in intel_pmu_check_counters_mask() argument
4958 bit = fls64(*fixed_cntr_mask); in intel_pmu_check_counters_mask()
4962 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); in intel_pmu_check_counters_mask()
4965 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED; in intel_pmu_check_counters_mask()
4970 u64 fixed_cntr_mask,
5097 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask)) in init_hybrid_pmu()
6342 u64 fixed_cntr_mask, in intel_pmu_check_event_constraints() argument
6381 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED); in intel_pmu_check_event_constraints()