Home
last modified time | relevance | path

Searched refs:fbdiv (Results 1 – 25 of 32) sorted by relevance

12

/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-pll.c83 unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */ member
95 unsigned int fbdiv; member
102 u32 fbdiv; member
107 char fbdiv; member
118 .fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \
125 .fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \
130 .fbdiv = JH7110_PLL##_idx##_FBDIV_SHIFT, \
149 u32 fbdiv; member
163 .fbdiv = 125,
169 .fbdiv = 125,
[all …]
/linux/drivers/clk/zynqmp/
H A Dpll.c104 u32 fbdiv; in zynqmp_pll_determine_rate() local
117 fbdiv = DIV_ROUND_CLOSEST(req->rate, req->best_parent_rate); in zynqmp_pll_determine_rate()
118 if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) { in zynqmp_pll_determine_rate()
119 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); in zynqmp_pll_determine_rate()
120 req->rate = req->best_parent_rate * fbdiv; in zynqmp_pll_determine_rate()
139 u32 fbdiv, data; in zynqmp_pll_recalc_rate() local
145 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); in zynqmp_pll_recalc_rate()
156 rate = parent_rate * fbdiv; in zynqmp_pll_recalc_rate()
183 u32 fbdiv; in zynqmp_pll_set_rate() local
209 fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); in zynqmp_pll_set_rate()
[all …]
/linux/drivers/clk/zynq/
H A Dpll.c54 u32 fbdiv; in zynq_pll_determine_rate() local
56 fbdiv = DIV_ROUND_CLOSEST(req->rate, req->best_parent_rate); in zynq_pll_determine_rate()
57 if (fbdiv < PLL_FBDIV_MIN) in zynq_pll_determine_rate()
58 fbdiv = PLL_FBDIV_MIN; in zynq_pll_determine_rate()
59 else if (fbdiv > PLL_FBDIV_MAX) in zynq_pll_determine_rate()
60 fbdiv = PLL_FBDIV_MAX; in zynq_pll_determine_rate()
62 req->rate = req->best_parent_rate * fbdiv; in zynq_pll_determine_rate()
77 u32 fbdiv; in zynq_pll_recalc_rate() local
83 fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
86 return parent_rate * fbdiv; in zynq_pll_recalc_rate()
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-pll.c78 unsigned int fbdiv; member
91 return FIELD_PREP(PLLCTRL_FBDIV_MASK, ctrl->fbdiv) | in sg2042_pll_ctrl_encode()
100 ctrl->fbdiv = FIELD_GET(PLLCTRL_FBDIV_MASK, reg_value); in sg2042_pll_ctrl_decode()
156 numerator = (u64)parent_rate * ctrl_table.fbdiv; in sg2042_pll_recalc_rate()
188 unsigned int fbdiv, in sg2042_pll_get_postdiv_1_2() argument
212 tmp0 *= fbdiv; in sg2042_pll_get_postdiv_1_2()
256 unsigned int fbdiv, refdiv, postdiv1, postdiv2; in sg2042_get_pll_ctl_setting() local
281 for (fbdiv = FBDIV_MIN; fbdiv < FBDIV_MAX + 1; fbdiv++) { in sg2042_get_pll_ctl_setting()
286 foutvco = parent_rate * fbdiv; in sg2042_get_pll_ctl_setting()
292 fbdiv, refdiv, in sg2042_get_pll_ctl_setting()
[all …]
H A Dclk-sg2044-pll.c118 unsigned long fbdiv) in sg2044_pll_calc_vco_rate() argument
120 u64 numerator = parent_rate * fbdiv; in sg2044_pll_calc_vco_rate()
127 unsigned long fbdiv, in sg2044_pll_calc_rate() argument
133 numerator = parent_rate * fbdiv; in sg2044_pll_calc_rate()
169 unsigned int fbdiv, in sg2042_pll_compute_postdiv() argument
180 refdiv, fbdiv, in sg2042_pll_compute_postdiv()
212 unsigned int refdiv, fbdiv, postdiv1, postdiv2; in sg2044_compute_pll_setting() local
217 for_each_pll_limit_range(fbdiv, &limits[PLL_LIMIT_FBDIV]) { in sg2044_compute_pll_setting()
220 refdiv, fbdiv); in sg2044_compute_pll_setting()
226 refdiv, fbdiv, in sg2044_compute_pll_setting()
[all …]
/linux/drivers/clk/pistachio/
H A Dclk-pll.c215 vco *= (params->fbdiv << 24) + params->frac; in pll_gf40lp_frac_set_rate()
234 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT); in pll_gf40lp_frac_set_rate()
277 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
281 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; in pll_gf40lp_frac_recalc_rate()
293 rate *= (fbdiv << 24) + frac; in pll_gf40lp_frac_recalc_rate()
295 rate *= (fbdiv << 24); in pll_gf40lp_frac_recalc_rate()
370 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
402 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) | in pll_gf40lp_laint_set_rate()
417 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
422 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; in pll_gf40lp_laint_recalc_rate()
[all …]
H A Dclk.h98 unsigned long long fbdiv; member
/linux/drivers/clk/mmp/
H A Dclk-pll.c49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
59 fbdiv = (val >> pll->shift) & 0x1ff; in mmp_clk_pll_recalc_rate()
62 fbdiv = 2; in mmp_clk_pll_recalc_rate()
74 rate *= 2 * fbdiv; in mmp_clk_pll_recalc_rate()
88 rate *= fbdiv + 2; in mmp_clk_pll_recalc_rate()
/linux/drivers/clk/axs10x/
H A Di2s_pll_clock.c27 unsigned int fbdiv; member
102 unsigned int idiv, fbdiv, odiv; in i2s_pll_recalc_rate() local
105 fbdiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_FBDIV_REG)); in i2s_pll_recalc_rate()
108 return ((parent_rate / idiv) * fbdiv) / odiv; in i2s_pll_recalc_rate()
145 i2s_pll_write(clk, PLL_FBDIV_REG, pll_cfg[i].fbdiv); in i2s_pll_set_rate()
H A Dpll_clock.c69 u32 fbdiv; member
139 u32 idiv, fbdiv, odiv; in axs10x_pll_recalc_rate() local
143 fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV)); in axs10x_pll_recalc_rate()
146 rate = (u64)parent_rate * fbdiv; in axs10x_pll_recalc_rate()
187 axs10x_encode_div(pll_cfg[i].fbdiv, 0)); in axs10x_pll_set_rate()
/linux/drivers/clk/berlin/
H A Dberlin2-pll.c46 u32 val, fbdiv, rfdiv, vcodivsel, vcodiv; in berlin2_pll_recalc_rate() local
50 fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK; in berlin2_pll_recalc_rate()
66 rate *= fbdiv * map->mult; in berlin2_pll_recalc_rate()
/linux/drivers/clk/rockchip/
H A Dclk-pll.c150 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) in rockchip_rk3036_pll_get_params()
177 rate64 *= cur.fbdiv; in rockchip_rk3036_pll_recalc_rate()
206 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
221 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
325 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
328 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
331 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3036_pll_init()
632 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) in rockchip_rk3399_pll_get_params()
661 rate64 *= cur.fbdiv; in rockchip_rk3399_pll_recalc_rate()
690 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3399_pll_set_params()
[all …]
/linux/drivers/clk/
H A Dclk-sp7021.c399 u32 fbdiv; in sp_pll_calc_div() local
402 fbdiv = DIV_ROUND_CLOSEST(rate, clk->brate); in sp_pll_calc_div()
403 if (fbdiv > max) in sp_pll_calc_div()
404 fbdiv = max; in sp_pll_calc_div()
406 return fbdiv; in sp_pll_calc_div()
469 u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1; in sp_pll_recalc_rate() local
471 ret = clk->brate * fbdiv; in sp_pll_recalc_rate()
493 u32 fbdiv = sp_pll_calc_div(clk, rate); in sp_pll_set_rate() local
497 reg |= ((fbdiv - 1) << clk->div_shift) & mask; in sp_pll_set_rate()
H A Dclk-hsdk-pll.c49 u32 fbdiv; member
142 val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; in hsdk_pll_set_cfg()
172 u32 idiv, fbdiv, odiv; in hsdk_pll_recalc_rate() local
190 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT)); in hsdk_pll_recalc_rate()
194 rate = (u64)parent_rate * fbdiv; in hsdk_pll_recalc_rate()
H A Dclk-axm5516.c52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
57 fbdiv = ((control >> 4) & 0xfff) + 3; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
H A Dclk-bm1880.c477 u32 fbdiv, refdiv; in bm1880_pll_rate_calc() local
480 fbdiv = (regval >> 16) & 0xfff; in bm1880_pll_rate_calc()
485 numerator = parent_rate * fbdiv; in bm1880_pll_rate_calc()
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-dsidphy.c243 u16 fbdiv; member
399 inno->pll.fbdiv = best_fbdiv; in inno_dsidphy_pll_calc_rate()
428 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); in inno_dsidphy_mipi_mode_enable()
430 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_dsidphy_mipi_mode_enable()
603 u16 fbdiv = 28; in inno_dsidphy_lvds_mode_enable() local
618 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv)); in inno_dsidphy_lvds_mode_enable()
620 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); in inno_dsidphy_lvds_mode_enable()
/linux/drivers/gpu/drm/radeon/
H A Drv740_dpm.c132 u32 fbdiv; in rv740_populate_sclk_value() local
144 fbdiv = (u32) tmp; in rv740_populate_sclk_value()
154 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); in rv740_populate_sclk_value()
164 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in rv740_populate_sclk_value()
H A Drv730_dpm.c51 u32 fbdiv; in rv730_populate_sclk_value() local
69 fbdiv = (u32) tmp; in rv730_populate_sclk_value()
85 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); in rv730_populate_sclk_value()
95 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); in rv730_populate_sclk_value()
H A Drs780_dpm.c212 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv() local
214 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
217 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
/linux/sound/soc/codecs/
H A Dcs48l32.c1602 int refdiv, fref, fout, lockdet_thr, fbdiv, fllgcd; in cs48l32_fllhj_apply() local
1627 fbdiv = 256; in cs48l32_fllhj_apply()
1629 fbdiv = 4; in cs48l32_fllhj_apply()
1633 fbdiv = (frac) ? 16 : 2; in cs48l32_fllhj_apply()
1637 fbdiv = 1; in cs48l32_fllhj_apply()
1658 while (ratio / fbdiv < min_n) { in cs48l32_fllhj_apply()
1659 fbdiv /= 2; in cs48l32_fllhj_apply()
1660 if (fbdiv < min_n) { in cs48l32_fllhj_apply()
1661 cs48l32_fll_err(fll, "FBDIV (%u) < minimum N (%u)\n", fbdiv, min_n); in cs48l32_fllhj_apply()
1665 while (frac && (ratio / fbdiv > max_ in cs48l32_fllhj_apply()
[all...]
H A Dmadera.c4410 int refdiv, fref, fout, lockdet_thr, fbdiv, hp, fast_clk, fllgcd; in madera_fllhj_disable()
4434 fbdiv = 256; in madera_fllhj_apply()
4436 fbdiv = 4; in madera_fllhj_apply()
4440 fbdiv = 1; in madera_fllhj_apply()
4444 fbdiv = 1; in madera_fllhj_apply()
4469 while (ratio / fbdiv < min_n) { in madera_fllhj_apply()
4470 fbdiv /= 2; in madera_fllhj_apply()
4471 if (fbdiv < 1) { in madera_fllhj_apply()
4472 madera_fll_err(fll, "FBDIV (%d) must be >= 1\n", fbdiv); in madera_fllhj_apply()
4476 while (frac && (ratio / fbdiv > max_ in madera_fllhj_apply()
4424 int refdiv, fref, fout, lockdet_thr, fbdiv, hp, fast_clk, fllgcd; madera_fllhj_apply() local
[all...]
/linux/drivers/clk/ralink/
H A Dclk-mt7621.c262 u32 pll, prediv, fbdiv; in mt7621_cpu_recalc_rate() local
278 fbdiv = FIELD_GET(CPU_PLL_FBDIV_MASK, pll); in mt7621_cpu_recalc_rate()
280 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; in mt7621_cpu_recalc_rate()
/linux/drivers/clk/xilinx/
H A Dxlnx_vcu.c93 u32 fbdiv; member
282 if (xvcu_pll_cfg[i].fbdiv == div) in xvcu_find_cfg()
301 vcu_pll_ctrl |= FIELD_PREP(VCU_PLL_CTRL_FBDIV, cfg->fbdiv); in xvcu_pll_set_div()
/linux/arch/arm/common/
H A Dsa1111.c1184 unsigned int skcdr, fbdiv, ipdiv, opdiv; in __sa1111_pll_clock() local
1188 fbdiv = (skcdr & 0x007f) + 2; in __sa1111_pll_clock()
1192 return 3686400 * fbdiv / (ipdiv * opdiv); in __sa1111_pll_clock()

12