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Searched refs:f32_cntl (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvpe_v6_1.c76 uint32_t i, f32_cntl; in vpe_v6_1_halt() local
79 f32_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL)); in vpe_v6_1_halt()
80 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, halt ? 1 : 0); in vpe_v6_1_halt()
81 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, halt ? 1 : 0); in vpe_v6_1_halt()
82 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL), f32_cntl); in vpe_v6_1_halt()
159 uint32_t f32_offset, f32_cntl; in vpe_v6_1_load_microcode() local
162 f32_cntl = RREG32(f32_offset); in vpe_v6_1_load_microcode()
163 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0); in vpe_v6_1_load_microcode()
164 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0); in vpe_v6_1_load_microcode()
167 adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl; in vpe_v6_1_load_microcode()
H A Dsdma_v5_0.c600 u32 f32_cntl = 0, phase_quantum = 0; in sdma_v5_0_ctx_switch_enable() local
629 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_0_ctx_switch_enable()
630 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_0_ctx_switch_enable()
643 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_0_ctx_switch_enable()
658 u32 f32_cntl; in sdma_v5_0_enable() local
672 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_enable()
673 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_0_enable()
674 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_0_enable()
1560 u32 f32_cntl, freeze, cntl, stat1_reg; in sdma_v5_0_stop_queue() local
1595 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_stop_queue()
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H A Dsdma_v5_2.c450 u32 f32_cntl, phase_quantum = 0; in sdma_v5_2_ctx_switch_enable() local
488 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_2_ctx_switch_enable()
489 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_2_ctx_switch_enable()
491 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_2_ctx_switch_enable()
507 u32 f32_cntl; in sdma_v5_2_enable() local
519 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_enable()
520 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_2_enable()
521 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_2_enable()
1468 u32 f32_cntl, freeze, cntl, stat1_reg; in sdma_v5_2_stop_queue() local
1504 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_stop_queue()
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H A Dsdma_v6_0.c432 u32 f32_cntl; in sdma_v6_0_ctxempty_int_enable() local
437 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL)); in sdma_v6_0_ctxempty_int_enable()
438 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v6_0_ctxempty_int_enable()
440 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); in sdma_v6_0_ctxempty_int_enable()
455 u32 f32_cntl; in sdma_v6_0_enable() local
467 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); in sdma_v6_0_enable()
468 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v6_0_enable()
469 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); in sdma_v6_0_enable()