Home
last modified time | relevance | path

Searched refs:event_ctrl (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_ddrc_pmu.c77 u32 event_ctrl; member
177 val = readl(ddrc_pmu->base + regs->event_ctrl); in hisi_ddrc_pmu_enable_counter()
179 writel(val, ddrc_pmu->base + regs->event_ctrl); in hisi_ddrc_pmu_enable_counter()
188 val = readl(ddrc_pmu->base + regs->event_ctrl); in hisi_ddrc_pmu_disable_counter()
190 writel(val, ddrc_pmu->base + regs->event_ctrl); in hisi_ddrc_pmu_disable_counter()
434 .event_ctrl = DDRC_EVENT_CTRL,
452 .event_ctrl = DDRC_V2_EVENT_CTRL,
470 .event_ctrl = DDRC_V2_EVENT_CTRL,
H A Dhisi_uncore_mn_pmu.c46 u32 event_ctrl; member
133 val = readl(mn_pmu->base + reg_info->event_ctrl); in hisi_mn_pmu_enable_counter()
135 writel(val, mn_pmu->base + reg_info->event_ctrl); in hisi_mn_pmu_enable_counter()
144 val = readl(mn_pmu->base + reg_info->event_ctrl); in hisi_mn_pmu_disable_counter()
146 writel(val, mn_pmu->base + reg_info->event_ctrl); in hisi_mn_pmu_disable_counter()
348 .event_ctrl = HISI_MN_EVENT_CTRL_REG,
H A Dhisi_uncore_sllc_pmu.c81 u32 event_ctrl; member
278 val = readl(sllc_pmu->base + regs->event_ctrl); in hisi_sllc_pmu_enable_counter()
280 writel(val, sllc_pmu->base + regs->event_ctrl); in hisi_sllc_pmu_enable_counter()
289 val = readl(sllc_pmu->base + regs->event_ctrl); in hisi_sllc_pmu_disable_counter()
291 writel(val, sllc_pmu->base + regs->event_ctrl); in hisi_sllc_pmu_disable_counter()
415 .event_ctrl = SLLC_EVENT_CTRL,
436 .event_ctrl = SLLC_V3_EVENT_CTRL,