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Searched refs:event_base (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/clocksource/
H A Dtimer-qcom.c34 static void __iomem *event_base; variable
42 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_interrupt()
44 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_interrupt()
53 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_set_next_event()
56 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_set_next_event()
58 writel_relaxed(ctrl, event_base + TIMER_CLEAR); in msm_timer_set_next_event()
59 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); in msm_timer_set_next_event()
65 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); in msm_timer_set_next_event()
73 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_shutdown()
75 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_shutdown()
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/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_l3c_pmu.c143 event->hw.event_base = (unsigned long)hisi_l3c_pmu->ext_base[ext - 1]; in hisi_l3c_pmu_get_event_idx()
145 event->hw.event_base = (unsigned long)l3c_pmu->base; in hisi_l3c_pmu_get_event_idx()
160 return readl((void __iomem *)hwc->event_base + reg); in hisi_l3c_pmu_event_readl()
165 writel(val, (void __iomem *)hwc->event_base + reg); in hisi_l3c_pmu_event_writel()
170 return readq((void __iomem *)hwc->event_base + reg); in hisi_l3c_pmu_event_readq()
175 writeq(val, (void __iomem *)hwc->event_base + reg); in hisi_l3c_pmu_event_writeq()
H A Dhisi_pcie_pmu.c391 hwc->event_base = HISI_PCIE_EXT_CNT; in hisi_pcie_pmu_event_init()
393 hwc->event_base = HISI_PCIE_CNT; in hisi_pcie_pmu_event_init()
415 return hisi_pcie_pmu_readq(pcie_pmu, event->hw.event_base, idx); in hisi_pcie_pmu_read_counter()
551 hisi_pcie_pmu_writeq(pcie_pmu, hwc->event_base, idx, prev_cnt); in hisi_pcie_pmu_start()
/linux/arch/x86/events/intel/
H A Duncore_discovery.c541 hwc->event_base = uncore_pci_perf_ctr(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
552 hwc->event_base = box_ctl + uncore_pci_perf_ctr(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
557 hwc->event_base = box_ctl + box->pmu->type->perf_ctr + hwc->idx; in intel_generic_uncore_assign_hw_event()
617 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); in intel_generic_uncore_pci_read_counter()
618 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1); in intel_generic_uncore_pci_read_counter()
H A Duncore.c154 rdmsrq(event->hw.event_base, count); in uncore_msr_read_counter()
171 if (!uncore_mmio_is_valid_offset(box, event->hw.event_base)) in uncore_mmio_read_counter()
174 return readq(box->io_addr + event->hw.event_base); in uncore_mmio_read_counter()
263 hwc->event_base = uncore_fixed_ctr(box); in uncore_assign_hw_event()
272 hwc->event_base = uncore_perf_ctr(box, hwc->idx); in uncore_assign_hw_event()
790 event->hw.event_base = uncore_freerunning_counter(box, event); in uncore_pmu_event_init()
H A Duncore_snb.c978 event->hw.event_base = base; in snb_uncore_imc_event_init()
1035 return (u64)readl(box->io_addr + hwc->event_base); in snb_uncore_imc_read_counter()
H A Duncore_snbep.c601 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); in snbep_uncore_pci_read_counter()
602 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1); in snbep_uncore_pci_read_counter()
H A Dcore.c3159 wrmsrq(event->hw.event_base, 0); in intel_pmu_save_and_restart()
/linux/arch/x86/events/amd/
H A Duncore.c153 rdmsrq(hwc->event_base, new); in amd_uncore_read()
173 wrmsrq(hwc->event_base, (u64)local64_read(&hwc->prev_count)); in amd_uncore_start()
235 hwc->event_base = pmu->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()
948 wrmsrq(hwc->event_base, (u64)local64_read(&hwc->prev_count)); in amd_uncore_umc_start()
969 rdmsrl(hwc->event_base, new); in amd_uncore_umc_read()
978 wrmsrl(hwc->event_base, 0); in amd_uncore_umc_read()
/linux/arch/loongarch/kernel/
H A Dperf_event.c274 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base) | in loongarch_pmu_enable_event()
547 event->hw.event_base = 0xffffffff; in loongarch_pmu_event_init()
786 hwc->event_base = loongarch_pmu_perf_event_encode(pev); in __hw_perf_event_init()
/linux/arch/sparc/kernel/
H A Dperf_event.c1356 events[n] = group->hw.event_base; in collect_events()
1365 events[n] = event->hw.event_base; in collect_events()
1385 cpuc->events[n0] = event->hw.event_base; in sparc_pmu_add()
1455 hwc->event_base = perf_event_encode(pmap); in sparc_pmu_event_init()
1461 hwc->event_base = attr->config; in sparc_pmu_event_init()
1481 events[n] = hwc->event_base; in sparc_pmu_event_init()
/linux/drivers/fpga/
H A Ddfl-fme-perf.c788 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); in fme_perf_event_destroy()
826 hwc->event_base = evtype; in fme_perf_event_init()
844 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); in fme_perf_event_update()
858 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); in fme_perf_event_start()
/linux/drivers/dma/idxd/
H A Dperfmon.c101 hwc->event_base = ioread64(CNTRCFG_REG(idxd, idx)); in perfmon_assign_hw_event()
189 event->hw.event_base = ioread64(PERFMON_TABLE_OFFSET(idxd)); in perfmon_pmu_event_init()
/linux/arch/x86/events/
H A Dcore.c132 if (unlikely(!hwc->event_base)) in x86_perf_event_update()
1251 hwc->event_base = 0; in x86_assign_hw_event()
1260 hwc->event_base = x86_pmu_fixed_ctr_addr(idx - INTEL_PMC_IDX_FIXED); in x86_assign_hw_event()
1267 hwc->event_base = x86_pmu_event_addr(hwc->idx); in x86_assign_hw_event()
1405 if (unlikely(!hwc->event_base)) in x86_perf_event_set_period()
1443 wrmsrq(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()
/linux/arch/powerpc/perf/
H A Dimc-pmu.c562 event->hw.event_base = (u64)pcni->vbase + l_config; in nest_imc_event_init()
894 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK); in core_imc_event_init()
1043 return (__be64 *)event->hw.event_base; in get_event_base_addr()
/linux/drivers/perf/
H A Darm-ccn.c893 dt_cfg = hw->event_base; in arm_ccn_pmu_xp_dt_config()
947 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); in arm_ccn_pmu_xp_watchpoint_config()
990 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); in arm_ccn_pmu_xp_event_config()
1013 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port, in arm_ccn_pmu_node_event_config()
H A Driscv_pmu.c332 hwc->event_base = mapped_event; in riscv_pmu_event_init()
H A Dcxl_pmu.c653 hwc->event_base); in cxl_pmu_event_start()
746 hwc->event_base = event_idx; in cxl_pmu_event_add()
/linux/include/linux/
H A Dperf_event.h156 unsigned long event_base; member