| /linux/drivers/gpu/drm/radeon/ |
| H A D | trinity_dpm.c | 946 if ((old_rps->evclk != new_rps->evclk) || in trinity_set_vce_clock()
949 if (new_rps->evclk || new_rps->ecclk) in trinity_set_vce_clock()
953 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in trinity_set_vce_clock()
1457 u32 evclk, u32 ecclk, u16 *voltage) in trinity_get_vce_clock_voltage() argument
1464 if (((evclk == 0) && (ecclk == 0)) || in trinity_get_vce_clock_voltage()
1471 if ((evclk <= table->entries[i].evclk) && in trinity_get_vce_clock_voltage()
1507 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in trinity_apply_state_adjust_rules()
1510 new_rps->evclk = 0; in trinity_apply_state_adjust_rules()
1528 trinity_get_vce_clock_voltage(rdev, new_rps->evclk, new_rps->ecclk, &min_vce_voltage); in trinity_apply_state_adjust_rules()
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| H A D | kv_dpm.c | 748 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
752 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk); in kv_populate_vce_table()
755 table->entries[i].evclk, false, ÷rs); in kv_populate_vce_table()
1279 static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk) in kv_get_vce_boot_level() argument
1286 if (table->entries[i].evclk >= evclk) in kv_get_vce_boot_level()
1302 if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) { in kv_update_vce_dpm()
1309 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); in kv_update_vce_dpm()
1326 } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) { in kv_update_vce_dpm()
1951 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()
1954 new_rps->evclk = 0; in kv_apply_state_adjust_rules()
[all …]
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| H A D | si_dpm.c | 2871 u32 evclk, u32 ecclk, u16 *voltage) in si_get_vce_clock_voltage() argument
2878 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
2885 if ((evclk <= table->entries[i].evclk) && in si_get_vce_clock_voltage()
2944 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
2946 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
2949 rps->evclk = 0; in si_apply_state_adjust_rules()
5871 if ((old_rps->evclk != new_rps->evclk) || in si_set_vce_clock()
5874 if (new_rps->evclk || new_rps->ecclk) in si_set_vce_clock()
5878 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
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| H A D | r600_dpm.c | 1105 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = in r600_parse_extended_power_table()
1120 rdev->pm.dpm.vce_states[i].evclk = in r600_parse_extended_power_table()
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| H A D | ni.c | 2692 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) in tn_set_vce_clocks() argument
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | power_state.h | 181 unsigned long evclk; member
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu10_hwmgr.h | 131 uint32_t evclk; member
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| H A D | smu8_hwmgr.h | 147 uint32_t evclk; member
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| H A D | smu7_hwmgr.h | 73 uint32_t evclk; member
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| H A D | vega10_hwmgr.h | 101 uint32_t evclk; member
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| H A D | vega20_hwmgr.h | 118 uint32_t evclk; member
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| H A D | processpptables.c | 1252 vce_table->entries[i].evclk = ((unsigned long)entry->ucEVClkHigh << 16) in get_vce_clock_voltage_limit_table()
1688 …vce_state->evclk = ((uint32_t)vce_clock_info->ucEVClkHigh << 16) | le16_to_cpu(vce_clock_info->usE… in get_vce_state_table_entry()
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| H A D | process_pptables_v1_0.c | 1338 vce_state->evclk = le32_to_cpu(mm_dep_record->ulEClk); in ppt_get_vce_state_table_entry_v1_0()
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| H A D | vega10_hwmgr.c | 5068 *equal &= ((vega10_psa->vce_clks.evclk == vega10_psb->vce_clks.evclk) && in vega10_check_states_equal()
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| H A D | smu7_hwmgr.c | 4745 …*equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.e… in smu7_check_states_equal()
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | si_dpm.c | 3045 u32 evclk, u32 ecclk, u16 *voltage) in si_get_vce_clock_voltage() argument
3052 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
3059 if ((evclk <= table->entries[i].evclk) && in si_get_vce_clock_voltage()
3513 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
3515 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3518 rps->evclk = 0; in si_apply_state_adjust_rules()
7046 if ((old_rps->evclk != new_rps->evclk) || in si_set_vce_clock()
7049 dev_dbg(adev->dev, "set VCE clocks: %u, %u\n", new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
7051 if (new_rps->evclk || new_rps->ecclk) { in si_set_vce_clock()
7052 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
[all …]
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | soc15.c | 691 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc15_set_vce_clocks() argument
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| H A D | amdgpu.h | 671 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
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| H A D | amdgpu_kms.c | 1054 vce_clk_table.entries[i].eclk = vce_state->evclk; in amdgpu_info_ioctl()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | ci_smumgr.c | 1572 table->VceLevel[count].Frequency = vce_table->entries[count].evclk; in ci_populate_smc_vce_level()
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