Searched refs:ep0_state (Results 1 – 16 of 16) sorted by relevance
391 switch (bdc->ep0_state) { in setup_first_bd_ep0()417 ep0_state_string[bdc->ep0_state]); in setup_first_bd_ep0()670 if (bdc->ep0_state == WAIT_FOR_STATUS_START) { in ep0_queue()673 bdc->ep0_state = WAIT_FOR_STATUS_XMIT; in ep0_queue()877 bdc->ep0_state = WAIT_FOR_SETUP; in ep_set_halt()1071 __func__, ep0_state_string[bdc->ep0_state]); in bdc_xsf_ep0_setup_recv()1077 bdc->ep0_state = WAIT_FOR_STATUS_START; in bdc_xsf_ep0_setup_recv()1079 bdc->ep0_state = WAIT_FOR_DATA_START; in bdc_xsf_ep0_setup_recv()1084 __func__, ep0_state_string[bdc->ep0_state]); in bdc_xsf_ep0_setup_recv()1419 bdc->ep0_state = WAIT_FOR_DATA_START; in ep0_queue_zlp()[all …]
430 enum bdc_ep0_state ep0_state; member
41 switch (mtu->ep0_state) { in decode_ep0_state()150 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in ep0_stall_set()319 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in handle_test_mode()541 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in ep0_rx_state()593 mtu->ep0_state = MU3D_EP0_STATE_TX_END; in ep0_tx_state()629 mtu->ep0_state = MU3D_EP0_STATE_TX; in ep0_read_setup()633 mtu->ep0_state = MU3D_EP0_STATE_RX; in ep0_read_setup()715 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in mtu3_ep0_isr()730 switch (mtu->ep0_state) { in mtu3_ep0_isr()753 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in mtu3_ep0_isr()[all …]
351 enum mtu3_g_ep0_state ep0_state; member
722 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in mtu3_link_isr()
177 udc->ep0_state = ISP1760_CTRL_SETUP; in isp1760_udc_ctrl_send_status()224 udc->ep0_state = ISP1760_CTRL_SETUP; in isp1760_udc_ctrl_send_stall()344 if (ep->addr == 0 && udc->ep0_state != ISP1760_CTRL_DATA_OUT) { in isp1760_ep_rx_ready()347 udc->ep0_state); in isp1760_ep_rx_ready()385 if (ep->addr == 0 && udc->ep0_state != ISP1760_CTRL_DATA_IN) { in isp1760_ep_tx_complete()388 udc->ep0_state); in isp1760_ep_tx_complete()735 if (udc->ep0_state != ISP1760_CTRL_SETUP) { in isp1760_ep0_setup()743 udc->ep0_state = ISP1760_CTRL_STATUS; in isp1760_ep0_setup()745 udc->ep0_state = ISP1760_CTRL_DATA_IN; in isp1760_ep0_setup()747 udc->ep0_state = ISP1760_CTRL_DATA_OUT; in isp1760_ep0_setup()[all …]
82 enum isp1760_ctrl_state ep0_state; member
64 enum ep0_state { enum98 enum ep0_state ep0state;
388 enum ep0_state { enum459 enum ep0_state ep0state;
336 u32 ep0_state; /* Endpoint zero state */ member
503 u32 ep0_state; /* Endpoint zero state */ member
256 enum ep0_state { enum303 enum ep0_state state;
1209 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); in dwc2_hsotg_start_req()1212 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) in dwc2_hsotg_start_req()1378 switch (hsotg->ep0_state) { in dwc2_gadget_set_ep0_desc_chain()1395 hsotg->ep0_state); in dwc2_gadget_set_ep0_desc_chain()1501 hs->ep0_state == DWC2_EP0_DATA_OUT) in dwc2_hsotg_ep_queue()1946 hsotg->ep0_state = DWC2_EP0_STATUS_IN; in dwc2_hsotg_process_control()1949 hsotg->ep0_state = DWC2_EP0_DATA_IN; in dwc2_hsotg_process_control()1952 hsotg->ep0_state = DWC2_EP0_DATA_OUT; in dwc2_hsotg_process_control()2058 hsotg->ep0_state = DWC2_EP0_SETUP; in dwc2_hsotg_enqueue_setup()2331 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; in dwc2_hsotg_ep0_zlp()[all …]
407 enum musb_g_ep0_state ep0_state; member
2066 musb->ep0_state = MUSB_EP0_STAGE_SETUP; in musb_g_reset()
91 enum ep0_state { enum126 enum ep0_state state; /* P: lock */917 enum ep0_state state; in ep0_read()