Searched refs:ep0_state (Results 1 – 13 of 13) sorted by relevance
41 switch (mtu->ep0_state) { in decode_ep0_state()150 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in ep0_stall_set()319 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in handle_test_mode()541 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in ep0_rx_state()593 mtu->ep0_state = MU3D_EP0_STATE_TX_END; in ep0_tx_state()629 mtu->ep0_state = MU3D_EP0_STATE_TX; in ep0_read_setup()633 mtu->ep0_state = MU3D_EP0_STATE_RX; in ep0_read_setup()715 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in mtu3_ep0_isr()730 switch (mtu->ep0_state) { in mtu3_ep0_isr()753 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in mtu3_ep0_isr()[all …]
351 enum mtu3_g_ep0_state ep0_state; member
640 mtu->ep0_state = MU3D_EP0_STATE_SETUP; in mtu3_state_reset()
177 udc->ep0_state = ISP1760_CTRL_SETUP; in isp1760_udc_ctrl_send_status()224 udc->ep0_state = ISP1760_CTRL_SETUP; in isp1760_udc_ctrl_send_stall()344 if (ep->addr == 0 && udc->ep0_state != ISP1760_CTRL_DATA_OUT) { in isp1760_ep_rx_ready()347 udc->ep0_state); in isp1760_ep_rx_ready()385 if (ep->addr == 0 && udc->ep0_state != ISP1760_CTRL_DATA_IN) { in isp1760_ep_tx_complete()388 udc->ep0_state); in isp1760_ep_tx_complete()735 if (udc->ep0_state != ISP1760_CTRL_SETUP) { in isp1760_ep0_setup()743 udc->ep0_state = ISP1760_CTRL_STATUS; in isp1760_ep0_setup()745 udc->ep0_state = ISP1760_CTRL_DATA_IN; in isp1760_ep0_setup()747 udc->ep0_state = ISP1760_CTRL_DATA_OUT; in isp1760_ep0_setup()[all …]
82 enum isp1760_ctrl_state ep0_state; member
1031 udc->ep0_state = WAIT_FOR_SETUP; in fsl_ep_set_halt()1260 udc->ep0_state = WAIT_FOR_SETUP; in ep0stall()1277 if (udc->ep0_state != DATA_STATE_XMIT) in ep0_prime_status()1278 udc->ep0_state = WAIT_FOR_OUT_STATUS; in ep0_prime_status()1381 udc->ep0_state = DATA_STATE_XMIT; in ch9getstatus()1493 udc->ep0_state = (setup->bRequestType & USB_DIR_IN) in setup_received_irq()1499 if (udc->ep0_state == DATA_STATE_XMIT) in setup_received_irq()1511 udc->ep0_state = WAIT_FOR_OUT_STATUS; in setup_received_irq()1529 switch (udc->ep0_state) { in ep0_req_complete()1532 udc->ep0_state = WAIT_FOR_OUT_STATUS; in ep0_req_complete()[all …]
336 u32 ep0_state; /* Endpoint zero state */ member
504 u32 ep0_state; /* Endpoint zero state */ member
430 enum bdc_ep0_state ep0_state; member
221 bdc->ep0_state = WAIT_FOR_SETUP; in bdc_mem_init()
407 enum musb_g_ep0_state ep0_state; member
2066 musb->ep0_state = MUSB_EP0_STAGE_SETUP; in musb_g_reset()
1211 enum dwc2_ep0_state ep0_state; member