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Searched refs:engine_id (Results 1 – 25 of 77) sorted by relevance

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/linux/drivers/gpu/drm/nouveau/nvkm/falcon/
H A Dga100.c38 FLCN_DBG(falcon, "brom: %08x %08x", fw->engine_id, fw->ucode_id); in ga100_flcn_fw_signature()
41 if (fw->engine_id & 0x00000001) { in ga100_flcn_fw_signature()
44 if (fw->engine_id & 0x00000004) { in ga100_flcn_fw_signature()
47 if (fw->engine_id & 0x00000400) { in ga100_flcn_fw_signature()
H A Dga102.c118 nvkm_falcon_wr32(falcon, falcon->addr2 + 0x19c, fw->engine_id); in ga102_flcn_fw_boot()
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table_helper_struct.h40 bool (*engine_bp_to_atom)(enum engine_id engine_id,
57 uint8_t (*dig_encoder_sel_to_atom)(enum engine_id engine_id);
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dlink_encoder.h52 enum engine_id analog_engine;
89 enum engine_id preferred_engine;
90 enum engine_id analog_engine;
152 enum engine_id engine,
201 enum engine_id eng_id;
248 enum engine_id preferred_engine;
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_arcturus.c68 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
74 switch (engine_id) { in get_sdma_rlc_reg_offset()
78 engine_id); in get_sdma_rlc_reg_offset()
117 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
193 uint32_t engine_id, uint32_t queue_id, in kgd_arcturus_hqd_sdma_dump() argument
197 engine_id, queue_id); in kgd_arcturus_hqd_sdma_dump()
H A Damdgpu_amdkfd_gfx_v12.c77 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
83 switch (engine_id) { in get_sdma_rlc_reg_offset()
99 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
137 uint32_t engine_id, uint32_t queue_id, in hqd_sdma_dump_v12() argument
141 engine_id, queue_id); in hqd_sdma_dump_v12()
H A Damdgpu_amdkfd_gfx_v10_3.c130 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
136 switch (engine_id) { in get_sdma_rlc_reg_offset()
140 engine_id); in get_sdma_rlc_reg_offset()
163 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
429 uint32_t engine_id, uint32_t queue_id, in hqd_sdma_dump_v10_3() argument
433 engine_id, queue_id); in hqd_sdma_dump_v10_3()
H A Damdgpu_amdkfd_gc_9_4_3.c44 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset()
54 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
129 uint32_t engine_id, uint32_t queue_id, in kgd_gfx_v9_4_3_hqd_sdma_dump() argument
133 engine_id, queue_id); in kgd_gfx_v9_4_3_hqd_sdma_dump()
H A Damdgpu_amdkfd_arcturus.h26 uint32_t engine_id, uint32_t queue_id,
H A Damdgpu_amdkfd_gfx_v11.c126 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
132 switch (engine_id) { in get_sdma_rlc_reg_offset()
148 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
414 uint32_t engine_id, uint32_t queue_id, in hqd_sdma_dump_v11() argument
418 engine_id, queue_id); in hqd_sdma_dump_v11()
H A Damdgpu_amdkfd_gfx_v9.c181 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
187 switch (engine_id) { in get_sdma_rlc_reg_offset()
191 engine_id); in get_sdma_rlc_reg_offset()
206 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
454 uint32_t engine_id, uint32_t queue_id, in kgd_hqd_sdma_dump() argument
458 engine_id, queue_id); in kgd_hqd_sdma_dump()
H A Damdgpu_amdkfd_gfx_v10.c161 unsigned int engine_id, in get_sdma_rlc_reg_offset() argument
177 uint32_t retval = sdma_engine_reg_base[engine_id] in get_sdma_rlc_reg_offset()
180 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, in get_sdma_rlc_reg_offset()
443 uint32_t engine_id, uint32_t queue_id, in kgd_hqd_sdma_dump() argument
447 engine_id, queue_id); in kgd_hqd_sdma_dump()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_hw.h294 uint32_t engine_id; member
308 uint32_t engine_id,
316 uint32_t engine_id,
324 uint32_t engine_id,
332 uint32_t engine_id,
340 uint32_t engine_id,
H A Ddce_link_encoder.c173 encoder_control.engine_id = link_enc->base.analog_engine; in link_dac_encoder_control()
284 enum engine_id result; in dce110_get_dig_frontend()
623 enum engine_id engine) in get_frontend_source()
1064 cntl.engine_id = ENGINE_ID_UNKNOWN; in dce110_link_encoder_hw_init()
1182 cntl.engine_id = enc->preferred_engine; in dce110_link_encoder_enable_tmds_output()
1218 cntl.engine_id = enc->preferred_engine; in dce110_link_encoder_enable_lvds_output()
1272 cntl.engine_id = enc->preferred_engine; in dce110_link_encoder_enable_dp_output()
1311 cntl.engine_id = ENGINE_ID_UNKNOWN; in dce110_link_encoder_enable_dp_mst_output()
1351 cntl.engine_id = enc->preferred_engine; in dce60_link_encoder_enable_dp_output()
1390 cntl.engine_id = ENGINE_ID_UNKNOWN; in dce60_link_encoder_enable_dp_mst_output()
[all …]
/linux/drivers/gpu/drm/amd/display/include/
H A Daudio_types.h104 enum engine_id engine_id; member
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/
H A Dga102.c84 fw->engine_id = meta[1]; in ga102_gsp_booter_ctor()
103 FLCN_DBG(falcon, "brom: %08x %08x", fw->engine_id, fw->ucode_id); in ga102_gsp_fwsec_signature()
106 if (fw->engine_id & 0x00000400) { in ga102_gsp_fwsec_signature()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_bios_types.h105 enum engine_id engine_id,
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_factory.c455 static enum engine_id find_analog_engine(struct dc_link *link, struct graphics_object_id *enc) in find_analog_engine()
481 static bool analog_engine_supported(const enum engine_id engine_id) in analog_engine_supported() argument
483 return engine_id == ENGINE_ID_DACA || in analog_engine_supported()
484 engine_id == ENGINE_ID_DACB; in analog_engine_supported()
500 enum engine_id link_analog_engine; in construct_phy()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/acr/
H A Dga102.c108 .engine_id = lsfw->engine_id, in ga102_acr_wpr_build_lsb()
119 hdr->hs_fmc_params.engid_mask = lsfw->engine_id; in ga102_acr_wpr_build_lsb()
/linux/drivers/accel/habanalabs/common/
H A Dstate_dump.c167 u32 engine_id) in hl_print_resize_sync_engine() argument
170 hl_sync_engine_to_string(engine_type), engine_id); in hl_print_resize_sync_engine()
368 entry->engine_id); in hl_state_dump_print_syncs_single_block()
H A Ddevice.c2682 void hl_capture_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_of_engines, in hl_capture_razwi() argument
2701 memcpy(&razwi_info->razwi.engine_id[0], &engine_id[0], in hl_capture_razwi()
2708 void hl_handle_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_of_engines, in hl_handle_razwi() argument
2711 hl_capture_razwi(hdev, addr, engine_id, num_of_engines, flags); in hl_handle_razwi()
2789 pgf_info->page_fault.engine_id = eng_id; in hl_capture_page_fault()
2850 void hl_capture_engine_err(struct hl_device *hdev, u16 engine_id, u16 error_count) in hl_capture_engine_err() argument
2859 info->event.engine_id = engine_id; in hl_capture_engine_err()
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_sp.h588 u8 engine_id; member
760 u8 engine_id; member
1471 u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
1512 u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
/linux/drivers/gpu/drm/xe/
H A Dxe_hw_engine_types.h146 enum xe_hw_engine_id engine_id; member
/linux/include/uapi/drm/
H A Dhabanalabs_accel.h1165 __u16 engine_id[HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR]; member
1195 __u32 engine_id; member
1241 __u16 engine_id; member
1330 __u16 engine_id; member
/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dacr.h101 u32 engine_id; member

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