| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_engine_heartbeat.c | 26 static bool next_heartbeat(struct intel_engine_cs *engine) in next_heartbeat() argument
31 delay = READ_ONCE(engine->props.heartbeat_interval_ms); in next_heartbeat()
33 rq = engine->heartbeat.systole; in next_heartbeat()
45 delay == engine->defaults.heartbeat_interval_ms) { in next_heartbeat()
53 longer = READ_ONCE(engine->props.preempt_timeout_ms) * 2; in next_heartbeat()
54 longer = intel_clamp_heartbeat_interval_ms(engine, longer); in next_heartbeat()
65 mod_delayed_work(system_highpri_wq, &engine->heartbeat.work, delay + 1); in next_heartbeat()
82 static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq) in idle_pulse() argument
84 engine->wakeref_serial = READ_ONCE(engine->serial) + 1; in idle_pulse()
86 if (!engine->heartbeat.systole && intel_engine_has_heartbeat(engine)) in idle_pulse()
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| H A D | intel_engine_cs.c | 358 static void __sprint_engine_name(struct intel_engine_cs *engine) in __sprint_engine_name() argument
365 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", in __sprint_engine_name()
366 intel_engine_class_repr(engine->class), in __sprint_engine_name()
367 engine->instance) >= sizeof(engine->name)); in __sprint_engine_name()
370 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) in intel_engine_set_hwsp_writemask() argument
376 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS) in intel_engine_set_hwsp_writemask()
379 if (GRAPHICS_VER(engine->i915) >= 3) in intel_engine_set_hwsp_writemask()
380 ENGINE_WRITE(engine, RING_HWSTAM, mask); in intel_engine_set_hwsp_writemask()
382 ENGINE_WRITE16(engine, RING_HWSTAM, mask); in intel_engine_set_hwsp_writemask()
385 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) in intel_engine_sanitize_mmio() argument
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| H A D | mock_engine.c | 60 static struct intel_ring *mock_ring(struct intel_engine_cs *engine) in mock_ring() argument
75 ring->vma = create_ring_vma(engine->gt->ggtt, PAGE_SIZE); in mock_ring()
93 static struct i915_request *first_request(struct mock_engine *engine) in first_request() argument
95 return list_first_entry_or_null(&engine->hw_queue, in first_request()
106 intel_engine_signal_breadcrumbs(request->engine); in advance()
111 struct mock_engine *engine = timer_container_of(engine, t, hw_delay); in hw_delay_complete() local
115 spin_lock_irqsave(&engine->hw_lock, flags); in hw_delay_complete()
118 request = first_request(engine); in hw_delay_complete()
126 while ((request = first_request(engine))) { in hw_delay_complete()
128 mod_timer(&engine->hw_delay, in hw_delay_complete()
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| H A D | selftest_engine_heartbeat.c | 14 static void reset_heartbeat(struct intel_engine_cs *engine) in reset_heartbeat() argument
16 intel_engine_set_heartbeat(engine, in reset_heartbeat()
17 engine->defaults.heartbeat_interval_ms); in reset_heartbeat()
37 static int engine_sync_barrier(struct intel_engine_cs *engine) in engine_sync_barrier() argument
39 return timeline_sync(engine->kernel_context->timeline); in engine_sync_barrier()
90 static int __live_idle_pulse(struct intel_engine_cs *engine, in __live_idle_pulse() argument
96 GEM_BUG_ON(!intel_engine_pm_is_awake(engine)); in __live_idle_pulse()
106 err = i915_active_acquire_preallocate_barrier(&p->active, engine); in __live_idle_pulse()
116 GEM_BUG_ON(llist_empty(&engine->barrier_tasks)); in __live_idle_pulse()
118 err = fn(engine); in __live_idle_pulse()
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| H A D | intel_engine_pm.h | 17 intel_engine_pm_is_awake(const struct intel_engine_cs *engine) in intel_engine_pm_is_awake() argument
19 return intel_wakeref_is_active(&engine->wakeref); in intel_engine_pm_is_awake()
22 static inline void __intel_engine_pm_get(struct intel_engine_cs *engine) in __intel_engine_pm_get() argument
24 __intel_wakeref_get(&engine->wakeref); in __intel_engine_pm_get()
27 static inline void intel_engine_pm_get(struct intel_engine_cs *engine) in intel_engine_pm_get() argument
29 intel_wakeref_get(&engine->wakeref); in intel_engine_pm_get()
32 static inline bool intel_engine_pm_get_if_awake(struct intel_engine_cs *engine) in intel_engine_pm_get_if_awake() argument
34 return intel_wakeref_get_if_active(&engine->wakeref); in intel_engine_pm_get_if_awake()
37 static inline void intel_engine_pm_might_get(struct intel_engine_cs *engine) in intel_engine_pm_might_get() argument
39 if (!intel_engine_is_virtual(engine)) { in intel_engine_pm_might_get()
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| H A D | selftest_engine_pm.c | 76 struct intel_engine_cs *engine = ce->engine; in __measure_timestamps() local
77 u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5); in __measure_timestamps()
78 u32 offset = i915_ggtt_offset(engine->status_page.vma); in __measure_timestamps()
96 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000); in __measure_timestamps()
97 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004); in __measure_timestamps()
102 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016); in __measure_timestamps()
103 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012); in __measure_timestamps()
108 intel_engine_flush_submission(engine); in __measure_timestamps()
132 engine->name, sema[1], sema[3], sema[0], sema[4]); in __measure_timestamps()
139 static int __live_engine_timestamps(struct intel_engine_cs *engine) in __live_engine_timestamps() argument
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| H A D | selftest_hangcheck.c | 104 hang_create_request(struct hang *h, struct intel_engine_cs *engine) in hang_create_request() argument
157 rq = igt_request_alloc(h->ctx, engine); in hang_create_request()
226 intel_gt_chipset_flush(engine->gt); in hang_create_request()
228 if (rq->engine->emit_init_breadcrumb) { in hang_create_request()
229 err = rq->engine->emit_init_breadcrumb(rq); in hang_create_request()
238 err = rq->engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags); in hang_create_request()
288 struct intel_engine_cs *engine; in igt_hang_sanitycheck() local
299 for_each_engine(engine, gt, id) { in igt_hang_sanitycheck()
303 if (!intel_engine_can_store_dword(engine)) in igt_hang_sanitycheck()
306 rq = hang_create_request(&h, engine); in igt_hang_sanitycheck()
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| H A D | selftest_workarounds.c | 34 } engine[I915_NUM_ENGINES]; member
64 struct intel_engine_cs *engine; in reference_lists_init() local
73 for_each_engine(engine, gt, id) { in reference_lists_init()
74 struct i915_wa_list *wal = &lists->engine[id].wa_list; in reference_lists_init()
76 wa_init_start(wal, gt, "REF", engine->name); in reference_lists_init()
77 engine_init_workarounds(engine, wal); in reference_lists_init()
80 __intel_engine_init_ctx_wa(engine, in reference_lists_init()
81 &lists->engine[id].ctx_wa_list, in reference_lists_init()
89 struct intel_engine_cs *engine; in reference_lists_fini() local
92 for_each_engine(engine, gt, id) in reference_lists_fini()
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| H A D | intel_reset.c | 323 struct intel_engine_cs *engine; in __gen6_reset_engines() local
332 for_each_engine_masked(engine, gt, engine_mask, tmp) { in __gen6_reset_engines()
333 hw_mask |= engine->reset_domain; in __gen6_reset_engines()
354 static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine) in find_sfc_paired_vecs_engine() argument
358 GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS); in find_sfc_paired_vecs_engine()
360 vecs_id = _VECS((engine->instance) / 2); in find_sfc_paired_vecs_engine()
362 return engine->gt->engine[vecs_id]; in find_sfc_paired_vecs_engine()
375 static void get_sfc_forced_lock_data(struct intel_engine_cs *engine, in get_sfc_forced_lock_data() argument
378 switch (engine->class) { in get_sfc_forced_lock_data()
380 MISSING_CASE(engine->class); in get_sfc_forced_lock_data()
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| H A D | sysfs_engines.c | 17 struct intel_engine_cs *engine; member
22 return container_of(kobj, struct kobj_engine, base)->engine; in kobj_to_engine()
82 __caps_show(struct intel_engine_cs *engine, in __caps_show() argument
89 switch (engine->class) { in __caps_show()
124 struct intel_engine_cs *engine = kobj_to_engine(kobj); in caps_show() local
126 return __caps_show(engine, engine->uabi_capabilities, buf, true); in caps_show()
145 struct intel_engine_cs *engine = kobj_to_engine(kobj); in max_spin_store() local
170 clamped = intel_clamp_max_busywait_duration_ns(engine, duration); in max_spin_store()
174 WRITE_ONCE(engine->props.max_busywait_duration_ns, duration); in max_spin_store()
182 struct intel_engine_cs *engine = kobj_to_engine(kobj); in max_spin_show() local
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| H A D | selftest_execlists.c | 27 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4) argument
45 static int wait_for_submit(struct intel_engine_cs *engine, in wait_for_submit() argument
50 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
60 intel_engine_flush_submission(engine); in wait_for_submit()
61 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
71 static int wait_for_reset(struct intel_engine_cs *engine, in wait_for_reset() argument
79 intel_engine_flush_submission(engine); in wait_for_reset()
81 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
93 engine->name, in wait_for_reset()
103 engine->name, in wait_for_reset()
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| H A D | selftest_mocs.c | 24 static struct intel_context *mocs_context_create(struct intel_engine_cs *engine) in mocs_context_create() argument
28 ce = intel_context_create(engine); in mocs_context_create()
134 struct intel_gt *gt = rq->engine->gt; in read_mocs_table()
143 addr = mocs_offset(rq->engine); in read_mocs_table()
160 static int check_mocs_table(struct intel_engine_cs *engine, in check_mocs_table() argument
173 engine->name, i, **vaddr, expect); in check_mocs_table()
192 static int check_l3cc_table(struct intel_engine_cs *engine, in check_l3cc_table() argument
205 if (!mcr_range(engine->i915, reg) && **vaddr != expect) { in check_l3cc_table()
207 engine->name, i, **vaddr, expect); in check_l3cc_table()
238 if (!err && ce->engine->class == RENDER_CLASS) in check_mocs_engine()
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| H A D | selftest_engine_cs.c | 44 static i915_reg_t timestamp_reg(struct intel_engine_cs *engine) in timestamp_reg() argument
46 struct drm_i915_private *i915 = engine->i915; in timestamp_reg()
49 return RING_TIMESTAMP_UDW(engine->mmio_base); in timestamp_reg()
51 return RING_TIMESTAMP(engine->mmio_base); in timestamp_reg()
70 *cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine)); in write_timestamp()
86 obj = i915_gem_object_create_internal(ce->engine->i915, PAGE_SIZE); in create_empty_batch()
136 struct intel_engine_cs *engine; in perf_mi_bb_start() local
145 for_each_engine(engine, gt, id) { in perf_mi_bb_start()
146 struct intel_context *ce = engine->kernel_context; in perf_mi_bb_start()
151 if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0) in perf_mi_bb_start()
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| H A D | selftest_gt_pm.c | 39 static u32 read_timestamp(struct intel_engine_cs *engine) in read_timestamp() argument
41 struct drm_i915_private *i915 = engine->i915; in read_timestamp()
44 ENGINE_READ_FW(engine, RING_TIMESTAMP); in read_timestamp()
47 return ENGINE_READ_FW(engine, RING_TIMESTAMP_UDW); in read_timestamp()
49 return ENGINE_READ_FW(engine, RING_TIMESTAMP); in read_timestamp()
52 static void measure_clocks(struct intel_engine_cs *engine, in measure_clocks() argument
61 cycles[i] = -read_timestamp(engine); in measure_clocks()
66 cycles[i] += read_timestamp(engine); in measure_clocks()
82 struct intel_engine_cs *engine; in live_gt_clocks() local
98 for_each_engine(engine, gt, id) { in live_gt_clocks()
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| H A D | gen6_engine_cs.c | 58 intel_gt_scratch_offset(rq->engine->gt, in gen6_emit_post_sync_nonzero_flush()
92 intel_gt_scratch_offset(rq->engine->gt, in gen6_emit_flush_rcs()
153 *cs++ = intel_gt_scratch_offset(rq->engine->gt, in gen6_emit_breadcrumb_rcs()
292 intel_gt_scratch_offset(rq->engine->gt, in gen7_emit_flush_rcs()
377 GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); in gen6_emit_breadcrumb_xcs()
397 GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); in gen7_emit_breadcrumb_xcs()
425 void gen6_irq_enable(struct intel_engine_cs *engine) in gen6_irq_enable() argument
427 ENGINE_WRITE(engine, RING_IMR, in gen6_irq_enable()
428 ~(engine->irq_enable_mask | engine->irq_keep_mask)); in gen6_irq_enable()
431 ENGINE_POSTING_READ(engine, RING_IMR); in gen6_irq_enable()
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| /linux/drivers/gpu/drm/nouveau/nvkm/core/ |
| H A D | engine.c | 31 nvkm_engine_chsw_load(struct nvkm_engine *engine) in nvkm_engine_chsw_load() argument
33 if (engine->func->chsw_load) in nvkm_engine_chsw_load()
34 return engine->func->chsw_load(engine); in nvkm_engine_chsw_load()
39 nvkm_engine_reset(struct nvkm_engine *engine) in nvkm_engine_reset() argument
41 if (engine->func->reset) in nvkm_engine_reset()
42 return engine->func->reset(engine); in nvkm_engine_reset()
44 nvkm_subdev_fini(&engine->subdev, NVKM_POWEROFF); in nvkm_engine_reset()
45 return nvkm_subdev_init(&engine->subdev); in nvkm_engine_reset()
51 struct nvkm_engine *engine = *pengine; in nvkm_engine_unref() local
53 if (engine) { in nvkm_engine_unref()
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| /linux/drivers/video/fbdev/via/ |
| H A D | accel.c | 13 static int viafb_set_bpp(void __iomem *engine, u8 bpp) in viafb_set_bpp() argument
19 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; in viafb_set_bpp()
34 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp()
39 static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height, in hw_bitblt_1() argument
79 ret = viafb_set_bpp(engine, dst_bpp); in hw_bitblt_1()
91 writel(tmp, engine + 0x08); in hw_bitblt_1()
100 writel(tmp, engine + 0x0C); in hw_bitblt_1()
108 writel(tmp, engine + 0x10); in hw_bitblt_1()
111 writel(fg_color, engine + 0x18); in hw_bitblt_1()
114 writel(bg_color, engine + 0x1C); in hw_bitblt_1()
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| /linux/drivers/gpu/drm/i915/selftests/ |
| H A D | intel_scheduler_helpers.c | 21 struct intel_engine_cs *engine; in intel_selftest_find_any_engine() local
24 for_each_engine(engine, gt, id) in intel_selftest_find_any_engine()
25 return engine; in intel_selftest_find_any_engine()
31 int intel_selftest_modify_policy(struct intel_engine_cs *engine, in intel_selftest_modify_policy() argument
37 saved->reset = engine->i915->params.reset; in intel_selftest_modify_policy()
38 saved->flags = engine->flags; in intel_selftest_modify_policy()
39 saved->timeslice = engine->props.timeslice_duration_ms; in intel_selftest_modify_policy()
40 saved->preempt_timeout = engine->props.preempt_timeout_ms; in intel_selftest_modify_policy()
52 engine->i915->params.reset = 2; in intel_selftest_modify_policy()
53 engine->flags |= I915_ENGINE_WANT_FORCED_PREEMPTION; in intel_selftest_modify_policy()
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| H A D | i915_request.c | 54 struct intel_engine_cs *engine; in num_uabi_engines() local
58 for_each_uabi_engine(engine, i915) in num_uabi_engines()
255 request->engine->submit_request(request); in igt_request_rewind()
284 struct intel_engine_cs *engine; member
371 ce = i915_gem_context_get_engine(ctx, t->engine->legacy_idx); in __igt_breadcrumbs_smoketest()
412 t->engine->name); in __igt_breadcrumbs_smoketest()
415 intel_gt_set_wedged(t->engine->gt); in __igt_breadcrumbs_smoketest()
459 .engine = rcs0(i915), in mock_breadcrumbs_smoketest()
486 t.contexts[n] = mock_context(t.engine->i915, "mock"); in mock_breadcrumbs_smoketest()
571 struct intel_engine_cs *engine; in live_nop_request() local
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | base.c | 56 nvkm_gr_chsw_load(struct nvkm_engine *engine) in nvkm_gr_chsw_load() argument
58 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_chsw_load()
65 nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile) in nvkm_gr_tile() argument
67 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_tile()
91 struct nvkm_gr *gr = nvkm_gr(oclass->engine); in nvkm_gr_oclass_get()
115 struct nvkm_gr *gr = nvkm_gr(oclass->engine); in nvkm_gr_cclass_new()
122 nvkm_gr_intr(struct nvkm_engine *engine) in nvkm_gr_intr() argument
124 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_intr()
129 nvkm_gr_nonstall(struct nvkm_engine *engine) in nvkm_gr_nonstall() argument
131 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_nonstall()
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| /linux/drivers/gpu/drm/i915/ |
| H A D | i915_cmd_parser.c | 803 static bool validate_cmds_sorted(const struct intel_engine_cs *engine, in validate_cmds_sorted() argument
824 drm_err(&engine->i915->drm, in validate_cmds_sorted()
827 engine->name, engine->id, in validate_cmds_sorted()
839 static bool check_sorted(const struct intel_engine_cs *engine, in check_sorted() argument
851 drm_err(&engine->i915->drm, in check_sorted()
854 engine->name, engine->id, in check_sorted()
865 static bool validate_regs_sorted(struct intel_engine_cs *engine) in validate_regs_sorted() argument
870 for (i = 0; i < engine->reg_table_count; i++) { in validate_regs_sorted()
871 table = &engine->reg_tables[i]; in validate_regs_sorted()
872 if (!check_sorted(engine, table->regs, table->num_regs)) in validate_regs_sorted()
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| H A D | i915_pmu.c | 358 static void gen3_engine_sample(struct intel_engine_cs *engine, unsigned int period_ns) in gen3_engine_sample() argument
360 struct intel_engine_pmu *pmu = &engine->pmu; in gen3_engine_sample()
364 val = ENGINE_READ_FW(engine, RING_CTL); in gen3_engine_sample()
374 if (intel_engine_supports_stats(engine)) in gen3_engine_sample()
386 val = ENGINE_READ_FW(engine, RING_MI_MODE); in gen3_engine_sample()
393 static void gen2_engine_sample(struct intel_engine_cs *engine, unsigned int period_ns) in gen2_engine_sample() argument
395 struct intel_engine_pmu *pmu = &engine->pmu; in gen2_engine_sample()
398 tail = ENGINE_READ_FW(engine, RING_TAIL); in gen2_engine_sample()
399 head = ENGINE_READ_FW(engine, RING_HEAD); in gen2_engine_sample()
400 acthd = ENGINE_READ_FW(engine, ACTHD); in gen2_engine_sample()
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/dma/ |
| H A D | Kbuild | 2 nvkm-y += nvkm/engine/dma/base.o
3 nvkm-y += nvkm/engine/dma/nv04.o
4 nvkm-y += nvkm/engine/dma/nv50.o
5 nvkm-y += nvkm/engine/dma/gf100.o
6 nvkm-y += nvkm/engine/dma/gf119.o
7 nvkm-y += nvkm/engine/dma/gv100.o
9 nvkm-y += nvkm/engine/dma/user.o
10 nvkm-y += nvkm/engine/dma/usernv04.o
11 nvkm-y += nvkm/engine/dma/usernv50.o
12 nvkm-y += nvkm/engine/dma/usergf100.o
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/sec2/ |
| H A D | base.c | 40 nvkm_sec2_fini(struct nvkm_engine *engine, enum nvkm_suspend_state suspend) in nvkm_sec2_fini() argument
42 struct nvkm_sec2 *sec2 = nvkm_sec2(engine); in nvkm_sec2_fini()
43 struct nvkm_subdev *subdev = &sec2->engine.subdev; in nvkm_sec2_fini()
75 nvkm_sec2_init(struct nvkm_engine *engine) in nvkm_sec2_init() argument
77 struct nvkm_sec2 *sec2 = nvkm_sec2(engine); in nvkm_sec2_init()
78 struct nvkm_subdev *subdev = &sec2->engine.subdev; in nvkm_sec2_init()
96 nvkm_sec2_oneinit(struct nvkm_engine *engine) in nvkm_sec2_oneinit() argument
98 struct nvkm_sec2 *sec2 = nvkm_sec2(engine); in nvkm_sec2_oneinit()
99 struct nvkm_subdev *subdev = &sec2->engine.subdev; in nvkm_sec2_oneinit()
100 struct nvkm_intr *intr = &sec2->engine.subdev.device->mc->intr; in nvkm_sec2_oneinit()
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/ |
| H A D | nv31.c | 42 int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, align, in nv31_mpeg_object_bind()
71 spin_lock_irqsave(&mpeg->engine.lock, flags); in nv31_mpeg_chan_dtor()
74 spin_unlock_irqrestore(&mpeg->engine.lock, flags); in nv31_mpeg_chan_dtor()
87 struct nv31_mpeg *mpeg = nv31_mpeg(oclass->engine); in nv31_mpeg_chan_new()
99 spin_lock_irqsave(&mpeg->engine.lock, flags); in nv31_mpeg_chan_new()
104 spin_unlock_irqrestore(&mpeg->engine.lock, flags); in nv31_mpeg_chan_new()
113 nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile) in nv31_mpeg_tile() argument
115 struct nv31_mpeg *mpeg = nv31_mpeg(engine); in nv31_mpeg_tile()
116 struct nvkm_device *device = mpeg->engine.subdev.device; in nv31_mpeg_tile()
127 struct nvkm_subdev *subdev = &mpeg->engine.subdev; in nv31_mpeg_mthd_dma()
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