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Searched refs:enable_mask (Results 1 – 25 of 316) sorted by relevance

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/linux/drivers/clk/qcom/
H A Dgcc-msm8660.c46 .enable_mask = BIT(8),
125 .enable_mask = BIT(11),
141 .enable_mask = BIT(9),
176 .enable_mask = BIT(11),
192 .enable_mask = BIT(9),
227 .enable_mask = BIT(11),
243 .enable_mask = BIT(9),
278 .enable_mask = BIT(11),
294 .enable_mask = BIT(9),
329 .enable_mask = BIT(11),
[all …]
H A Dnwgcc-nord.c40 .enable_mask = BIT(0),
132 .enable_mask = BIT(0),
147 .enable_mask = BIT(0),
162 .enable_mask = BIT(0),
177 .enable_mask = BIT(0),
192 .enable_mask = BIT(0),
207 .enable_mask = BIT(0),
222 .enable_mask = BIT(0),
237 .enable_mask = BIT(0),
252 .enable_mask = BIT(0),
[all …]
H A Dgcc-sm8250.c40 .enable_mask = BIT(0),
79 .enable_mask = BIT(4),
96 .enable_mask = BIT(9),
1063 .enable_mask = BIT(0),
1078 .enable_mask = BIT(0),
1098 .enable_mask = BIT(0),
1116 .enable_mask = BIT(0),
1134 .enable_mask = BIT(0),
1154 .enable_mask = BIT(10),
1167 .enable_mask = BIT(0),
[all …]
H A Dgcc-mdm9615.c65 .enable_mask = BIT(0),
78 .enable_mask = BIT(4),
107 .enable_mask = BIT(8),
136 .enable_mask = BIT(11),
207 .enable_mask = BIT(11),
223 .enable_mask = BIT(9),
258 .enable_mask = BIT(11),
274 .enable_mask = BIT(9),
309 .enable_mask = BIT(11),
325 .enable_mask = BIT(9),
[all …]
H A Dgcc-ipq806x.c50 .enable_mask = BIT(0),
79 .enable_mask = BIT(4),
108 .enable_mask = BIT(8),
215 .enable_mask = BIT(14),
433 .enable_mask = BIT(11),
449 .enable_mask = BIT(9),
484 .enable_mask = BIT(11),
500 .enable_mask = BIT(9),
535 .enable_mask = BIT(11),
551 .enable_mask = BIT(9),
[all …]
H A Dgcc-sc7180.c40 .enable_mask = BIT(0),
93 .enable_mask = BIT(1),
111 .enable_mask = BIT(4),
129 .enable_mask = BIT(6),
147 .enable_mask = BIT(7),
833 .enable_mask = BIT(0),
851 .enable_mask = BIT(0),
871 .enable_mask = BIT(10),
884 .enable_mask = BIT(0),
899 .enable_mask = BIT(0),
[all …]
H A Dgcc-sc8280xp.c117 .enable_mask = BIT(0),
154 .enable_mask = BIT(2),
169 .enable_mask = BIT(4),
184 .enable_mask = BIT(7),
199 .enable_mask = BIT(8),
214 .enable_mask = BIT(9),
2529 .enable_mask = BIT(14),
2544 .enable_mask = BIT(21),
2559 .enable_mask = BIT(12),
2574 .enable_mask = BIT(13),
[all …]
H A Dmmcc-msm8960.c208 .enable_mask = BIT(2),
223 .enable_mask = BIT(0),
259 .enable_mask = BIT(2),
274 .enable_mask = BIT(0),
310 .enable_mask = BIT(2),
325 .enable_mask = BIT(0),
367 .enable_mask = BIT(2),
382 .enable_mask = BIT(0),
400 .enable_mask = BIT(8),
435 .enable_mask = BIT(2),
[all …]
H A Dgcc-sm6350.c39 .enable_mask = BIT(0),
100 .enable_mask = BIT(6),
139 .enable_mask = BIT(7),
805 .enable_mask = BIT(0),
825 .enable_mask = BIT(1),
845 .enable_mask = BIT(1),
865 .enable_mask = BIT(0),
885 .enable_mask = BIT(28),
900 .enable_mask = BIT(0),
916 .enable_mask = BIT(0),
[all …]
H A Decpricc-qdu1000.c66 .enable_mask = BIT(0),
96 .enable_mask = BIT(1),
744 .enable_mask = BIT(0),
762 .enable_mask = BIT(0),
780 .enable_mask = BIT(0),
798 .enable_mask = BIT(0),
816 .enable_mask = BIT(0),
834 .enable_mask = BIT(0),
852 .enable_mask = BIT(0),
870 .enable_mask = BIT(0),
[all …]
H A Dgcc-msm8996.c53 .enable_mask = BIT(0),
95 .enable_mask = BIT(0),
112 .enable_mask = BIT(2),
130 .enable_mask = BIT(4),
1181 .enable_mask = BIT(0),
1198 .enable_mask = BIT(0),
1215 .enable_mask = BIT(0),
1232 .enable_mask = BIT(0),
1245 .enable_mask = BIT(0),
1258 .enable_mask = BIT(0),
[all …]
H A Dgcc-msm8998.c42 .enable_mask = BIT(0),
113 .enable_mask = BIT(1),
184 .enable_mask = BIT(2),
255 .enable_mask = BIT(3),
326 .enable_mask = BIT(4),
1222 .enable_mask = BIT(0),
1235 .enable_mask = BIT(0),
1253 .enable_mask = BIT(0),
1271 .enable_mask = BIT(0),
1284 .enable_mask = BIT(0),
[all …]
H A Dgcc-sm7150.c45 .enable_mask = BIT(0),
100 .enable_mask = BIT(6),
117 .enable_mask = BIT(7),
972 .enable_mask = BIT(0),
987 .enable_mask = BIT(0),
1007 .enable_mask = BIT(1),
1025 .enable_mask = BIT(0),
1043 .enable_mask = BIT(0),
1063 .enable_mask = BIT(10),
1076 .enable_mask = BIT(0),
[all …]
H A Dgcc-sm6125.c46 .enable_mask = BIT(0),
89 .enable_mask = BIT(3),
106 .enable_mask = BIT(4),
123 .enable_mask = BIT(5),
140 .enable_mask = BIT(6),
170 .enable_mask = BIT(7),
200 .enable_mask = BIT(8),
230 .enable_mask = BIT(9),
1363 .enable_mask = BIT(0),
1378 .enable_mask = BIT(0),
[all …]
H A Dgcc-qcs615.c48 .enable_mask = BIT(0),
79 .enable_mask = BIT(3),
110 .enable_mask = BIT(4),
127 .enable_mask = BIT(6),
166 .enable_mask = BIT(7),
183 .enable_mask = BIT(8),
1055 .enable_mask = BIT(0),
1073 .enable_mask = BIT(0),
1091 .enable_mask = BIT(0),
1111 .enable_mask = BIT(0),
[all …]
H A Dgcc-x1e80100.c118 .enable_mask = BIT(0),
157 .enable_mask = BIT(4),
174 .enable_mask = BIT(7),
191 .enable_mask = BIT(8),
208 .enable_mask = BIT(9),
2409 .enable_mask = BIT(0),
2424 .enable_mask = BIT(0),
2439 .enable_mask = BIT(0),
2459 .enable_mask = BIT(0),
2479 .enable_mask = BIT(0),
[all …]
H A Dgcc-msm8976.c75 .enable_mask = BIT(0),
108 .enable_mask = BIT(2),
145 .enable_mask = BIT(4),
192 .enable_mask = BIT(5),
223 .enable_mask = BIT(7),
1658 .enable_mask = BIT(0),
1675 .enable_mask = BIT(0),
1693 .enable_mask = BIT(0),
1711 .enable_mask = BIT(0),
1729 .enable_mask = BIT(0),
[all …]
H A Dgcc-nord.c50 .enable_mask = BIT(0),
542 .enable_mask = BIT(0),
555 .enable_mask = BIT(0),
573 .enable_mask = BIT(0),
591 .enable_mask = BIT(0),
606 .enable_mask = BIT(14),
626 .enable_mask = BIT(13),
641 .enable_mask = BIT(8),
656 .enable_mask = BIT(12),
669 .enable_mask = BIT(12),
[all …]
H A Dgcc-ipq5018.c65 .enable_mask = BIT(0),
80 .enable_mask = BIT(2),
95 .enable_mask = BIT(5),
110 .enable_mask = BIT(6),
1337 .enable_mask = BIT(1),
1352 .enable_mask = BIT(1),
1367 .enable_mask = BIT(0),
1384 .enable_mask = BIT(0),
1402 .enable_mask = BIT(10),
1419 .enable_mask = BIT(0),
[all …]
H A Dgcc-qcs8300.c63 .enable_mask = BIT(0),
102 .enable_mask = BIT(1),
119 .enable_mask = BIT(4),
136 .enable_mask = BIT(7),
153 .enable_mask = BIT(9),
1348 .enable_mask = BIT(28),
1363 .enable_mask = BIT(0),
1383 .enable_mask = BIT(0),
1403 .enable_mask = BIT(0),
1423 .enable_mask = BIT(0),
[all …]
H A Dtcsrcc-nord.c32 .enable_mask = BIT(0),
49 .enable_mask = BIT(0),
66 .enable_mask = BIT(0),
83 .enable_mask = BIT(0),
100 .enable_mask = BIT(0),
117 .enable_mask = BIT(0),
134 .enable_mask = BIT(0),
151 .enable_mask = BIT(0),
168 .enable_mask = BIT(0),
185 .enable_mask = BIT(0),
[all …]
H A Dgcc-sc7280.c49 .enable_mask = BIT(0),
110 .enable_mask = BIT(1),
127 .enable_mask = BIT(9),
144 .enable_mask = BIT(4),
161 .enable_mask = BIT(8),
177 .enable_mask = BIT(17),
1235 .enable_mask = BIT(0),
1248 .enable_mask = BIT(0),
1263 .enable_mask = BIT(12),
1278 .enable_mask = BIT(11),
[all …]
H A Dgcc-sa8775p.c77 .enable_mask = BIT(0),
114 .enable_mask = BIT(1),
129 .enable_mask = BIT(4),
144 .enable_mask = BIT(5),
159 .enable_mask = BIT(7),
174 .enable_mask = BIT(9),
1689 .enable_mask = BIT(28),
1704 .enable_mask = BIT(0),
1724 .enable_mask = BIT(0),
1744 .enable_mask = BIT(0),
[all …]
H A Dgcc-sm4450.c59 .enable_mask = BIT(0),
120 .enable_mask = BIT(1),
149 .enable_mask = BIT(3),
166 .enable_mask = BIT(4),
183 .enable_mask = BIT(9),
200 .enable_mask = BIT(10),
1021 .enable_mask = BIT(12),
1036 .enable_mask = BIT(0),
1056 .enable_mask = BIT(1),
1076 .enable_mask = BIT(0),
[all …]
H A Dgcc-sm8350.c48 .enable_mask = BIT(0),
87 .enable_mask = BIT(4),
105 .enable_mask = BIT(9),
1244 .enable_mask = BIT(12),
1258 .enable_mask = BIT(11),
1273 .enable_mask = BIT(18),
1288 .enable_mask = BIT(0),
1308 .enable_mask = BIT(1),
1328 .enable_mask = BIT(0),
1348 .enable_mask = BIT(1),
[all …]

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