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Searched refs:enable_mask (Results 1 – 25 of 303) sorted by relevance

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/linux/drivers/clk/qcom/
H A Dgcc-msm8660.c46 .enable_mask = BIT(8),
125 .enable_mask = BIT(11),
141 .enable_mask = BIT(9),
176 .enable_mask = BIT(11),
192 .enable_mask = BIT(9),
227 .enable_mask = BIT(11),
243 .enable_mask = BIT(9),
278 .enable_mask = BIT(11),
294 .enable_mask = BIT(9),
329 .enable_mask = BIT(11),
[all …]
H A Dgcc-sm8250.c40 .enable_mask = BIT(0),
79 .enable_mask = BIT(4),
96 .enable_mask = BIT(9),
1063 .enable_mask = BIT(0),
1078 .enable_mask = BIT(0),
1098 .enable_mask = BIT(0),
1116 .enable_mask = BIT(0),
1134 .enable_mask = BIT(0),
1154 .enable_mask = BIT(10),
1167 .enable_mask = BIT(0),
[all …]
H A Dgcc-mdm9615.c65 .enable_mask = BIT(0),
78 .enable_mask = BIT(4),
107 .enable_mask = BIT(8),
136 .enable_mask = BIT(11),
207 .enable_mask = BIT(11),
223 .enable_mask = BIT(9),
258 .enable_mask = BIT(11),
274 .enable_mask = BIT(9),
309 .enable_mask = BIT(11),
325 .enable_mask = BIT(9),
[all …]
H A Dgcc-ipq806x.c50 .enable_mask = BIT(0),
79 .enable_mask = BIT(4),
108 .enable_mask = BIT(8),
215 .enable_mask = BIT(14),
433 .enable_mask = BIT(11),
449 .enable_mask = BIT(9),
484 .enable_mask = BIT(11),
500 .enable_mask = BIT(9),
535 .enable_mask = BIT(11),
551 .enable_mask = BIT(9),
[all …]
H A Dgcc-sc7180.c40 .enable_mask = BIT(0),
93 .enable_mask = BIT(1),
111 .enable_mask = BIT(4),
129 .enable_mask = BIT(6),
147 .enable_mask = BIT(7),
833 .enable_mask = BIT(0),
851 .enable_mask = BIT(0),
871 .enable_mask = BIT(10),
884 .enable_mask = BIT(0),
899 .enable_mask = BIT(0),
[all …]
H A Dgcc-sc8180x.c53 .enable_mask = BIT(0),
95 .enable_mask = BIT(1),
114 .enable_mask = BIT(4),
133 .enable_mask = BIT(7),
150 .enable_mask = BIT(9),
1400 .enable_mask = BIT(0),
1415 .enable_mask = BIT(0),
1435 .enable_mask = BIT(1),
1455 .enable_mask = BIT(0),
1475 .enable_mask = BIT(1),
[all …]
H A Dgcc-sc8280xp.c117 .enable_mask = BIT(0),
154 .enable_mask = BIT(2),
169 .enable_mask = BIT(4),
184 .enable_mask = BIT(7),
199 .enable_mask = BIT(8),
214 .enable_mask = BIT(9),
2529 .enable_mask = BIT(14),
2544 .enable_mask = BIT(21),
2559 .enable_mask = BIT(12),
2574 .enable_mask = BIT(13),
[all …]
H A Dgcc-sm6350.c39 .enable_mask = BIT(0),
100 .enable_mask = BIT(6),
139 .enable_mask = BIT(7),
805 .enable_mask = BIT(0),
825 .enable_mask = BIT(1),
845 .enable_mask = BIT(1),
865 .enable_mask = BIT(0),
885 .enable_mask = BIT(28),
900 .enable_mask = BIT(0),
916 .enable_mask = BIT(0),
[all …]
H A Decpricc-qdu1000.c67 .enable_mask = BIT(0),
97 .enable_mask = BIT(1),
745 .enable_mask = BIT(0),
763 .enable_mask = BIT(0),
781 .enable_mask = BIT(0),
799 .enable_mask = BIT(0),
817 .enable_mask = BIT(0),
835 .enable_mask = BIT(0),
853 .enable_mask = BIT(0),
871 .enable_mask = BIT(0),
[all …]
H A Dgcc-msm8996.c53 .enable_mask = BIT(0),
95 .enable_mask = BIT(0),
112 .enable_mask = BIT(2),
130 .enable_mask = BIT(4),
1181 .enable_mask = BIT(0),
1198 .enable_mask = BIT(0),
1215 .enable_mask = BIT(0),
1232 .enable_mask = BIT(0),
1245 .enable_mask = BIT(0),
1258 .enable_mask = BIT(0),
[all …]
H A Dgcc-msm8998.c42 .enable_mask = BIT(0),
113 .enable_mask = BIT(1),
184 .enable_mask = BIT(2),
255 .enable_mask = BIT(3),
326 .enable_mask = BIT(4),
1222 .enable_mask = BIT(0),
1235 .enable_mask = BIT(0),
1253 .enable_mask = BIT(0),
1271 .enable_mask = BIT(0),
1284 .enable_mask = BIT(0),
[all …]
H A Dgcc-sm6125.c46 .enable_mask = BIT(0),
89 .enable_mask = BIT(3),
106 .enable_mask = BIT(4),
123 .enable_mask = BIT(5),
140 .enable_mask = BIT(6),
170 .enable_mask = BIT(7),
200 .enable_mask = BIT(8),
230 .enable_mask = BIT(9),
1363 .enable_mask = BIT(0),
1378 .enable_mask = BIT(0),
[all …]
H A Dgcc-sm7150.c46 .enable_mask = BIT(0),
101 .enable_mask = BIT(6),
118 .enable_mask = BIT(7),
973 .enable_mask = BIT(0),
988 .enable_mask = BIT(0),
1008 .enable_mask = BIT(1),
1026 .enable_mask = BIT(0),
1044 .enable_mask = BIT(0),
1064 .enable_mask = BIT(10),
1077 .enable_mask = BIT(0),
[all …]
H A Dgcc-x1e80100.c113 .enable_mask = BIT(0),
152 .enable_mask = BIT(4),
169 .enable_mask = BIT(7),
186 .enable_mask = BIT(8),
203 .enable_mask = BIT(9),
2362 .enable_mask = BIT(0),
2377 .enable_mask = BIT(0),
2392 .enable_mask = BIT(0),
2412 .enable_mask = BIT(0),
2432 .enable_mask = BIT(0),
[all …]
H A Dgcc-qcs615.c49 .enable_mask = BIT(0),
80 .enable_mask = BIT(3),
111 .enable_mask = BIT(4),
128 .enable_mask = BIT(6),
167 .enable_mask = BIT(7),
184 .enable_mask = BIT(8),
1056 .enable_mask = BIT(0),
1074 .enable_mask = BIT(0),
1092 .enable_mask = BIT(0),
1112 .enable_mask = BIT(0),
[all …]
H A Dgcc-msm8976.c75 .enable_mask = BIT(0),
108 .enable_mask = BIT(2),
145 .enable_mask = BIT(4),
192 .enable_mask = BIT(5),
223 .enable_mask = BIT(7),
1658 .enable_mask = BIT(0),
1675 .enable_mask = BIT(0),
1693 .enable_mask = BIT(0),
1711 .enable_mask = BIT(0),
1729 .enable_mask = BIT(0),
[all …]
H A Dgcc-qcs8300.c64 .enable_mask = BIT(0),
103 .enable_mask = BIT(1),
120 .enable_mask = BIT(4),
137 .enable_mask = BIT(7),
154 .enable_mask = BIT(9),
1349 .enable_mask = BIT(28),
1364 .enable_mask = BIT(0),
1384 .enable_mask = BIT(0),
1404 .enable_mask = BIT(0),
1424 .enable_mask = BIT(0),
[all …]
H A Dgcc-sa8775p.c78 .enable_mask = BIT(0),
115 .enable_mask = BIT(1),
130 .enable_mask = BIT(4),
145 .enable_mask = BIT(5),
160 .enable_mask = BIT(7),
175 .enable_mask = BIT(9),
1690 .enable_mask = BIT(28),
1705 .enable_mask = BIT(0),
1725 .enable_mask = BIT(0),
1745 .enable_mask = BIT(0),
[all …]
H A Dgcc-sc7280.c49 .enable_mask = BIT(0),
110 .enable_mask = BIT(1),
127 .enable_mask = BIT(9),
144 .enable_mask = BIT(4),
161 .enable_mask = BIT(8),
177 .enable_mask = BIT(17),
1235 .enable_mask = BIT(0),
1248 .enable_mask = BIT(0),
1263 .enable_mask = BIT(12),
1278 .enable_mask = BIT(11),
[all …]
H A Dgcc-sm4450.c60 .enable_mask = BIT(0),
121 .enable_mask = BIT(1),
150 .enable_mask = BIT(3),
167 .enable_mask = BIT(4),
184 .enable_mask = BIT(9),
201 .enable_mask = BIT(10),
1022 .enable_mask = BIT(12),
1037 .enable_mask = BIT(0),
1057 .enable_mask = BIT(1),
1077 .enable_mask = BIT(0),
[all …]
H A Dgcc-sm8350.c48 .enable_mask = BIT(0),
87 .enable_mask = BIT(4),
105 .enable_mask = BIT(9),
1244 .enable_mask = BIT(12),
1258 .enable_mask = BIT(11),
1273 .enable_mask = BIT(18),
1288 .enable_mask = BIT(0),
1308 .enable_mask = BIT(1),
1328 .enable_mask = BIT(0),
1348 .enable_mask = BIT(1),
[all …]
H A Dgcc-qdu1000.c55 .enable_mask = BIT(0),
93 .enable_mask = BIT(1),
127 .enable_mask = BIT(2),
161 .enable_mask = BIT(3),
178 .enable_mask = BIT(4),
195 .enable_mask = BIT(5),
229 .enable_mask = BIT(6),
246 .enable_mask = BIT(7),
263 .enable_mask = BIT(8),
1033 .enable_mask = BIT(0),
[all …]
H A Dgcc-apq8084.c58 .enable_mask = BIT(0),
89 .enable_mask = BIT(1),
120 .enable_mask = BIT(4),
310 .enable_mask = BIT(0),
327 .enable_mask = BIT(0),
1353 .enable_mask = BIT(0),
1386 .enable_mask = BIT(26),
1402 .enable_mask = BIT(12),
1419 .enable_mask = BIT(17),
1435 .enable_mask = BIT(0),
[all …]
H A Dgcc-sm8450.c55 .enable_mask = BIT(0),
103 .enable_mask = BIT(2),
120 .enable_mask = BIT(3),
146 .enable_mask = BIT(4),
172 .enable_mask = BIT(9),
1272 .enable_mask = BIT(12),
1287 .enable_mask = BIT(11),
1302 .enable_mask = BIT(0),
1322 .enable_mask = BIT(1),
1342 .enable_mask = BIT(0),
[all …]
/linux/drivers/regulator/
H A D88pm886-regulator.c67 .enable_mask = BIT(0),
80 .enable_mask = BIT(1),
93 .enable_mask = BIT(2),
106 .enable_mask = BIT(3),
119 .enable_mask = BIT(4),
132 .enable_mask = BIT(5),
145 .enable_mask = BIT(6),
158 .enable_mask = BIT(7),
171 .enable_mask = BIT(0),
184 .enable_mask = BIT(1),
[all …]

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