Home
last modified time | relevance | path

Searched refs:emc_dbg (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) macro
108 emc_dbg(emc, EMA_UPDATES, "%s: (s=%u) EMA: %u\n", \
262 emc_dbg(emc, PER_TRAIN, "Periodic training starting\n"); in tegra210_emc_r21021_periodic_compensation()
311 emc_dbg(emc, EMA_WRITES, "0x%08x <= 0x%08x\n", in tegra210_emc_r21021_periodic_compensation()
368 u32 emc_dbg, emc_cfg_pipe_clk, emc_pin; in tegra210_emc_r21021_set_clock() local
376 emc_dbg(emc, INFO, "Running clock change.\n"); in tegra210_emc_r21021_set_clock()
413 emc_dbg = emc_readl(emc, EMC_DBG); in tegra210_emc_r21021_set_clock()
427 emc_dbg(emc, INFO, "Clock change version: %d\n", in tegra210_emc_r21021_set_clock()
429 emc_dbg(emc, INFO, "DRAM type = %d\n", dram_type); in tegra210_emc_r21021_set_clock()
430 emc_dbg(emc, INFO, "DRAM dev #: %u\n", emc->num_devices); in tegra210_emc_r21021_set_clock()
[all …]
H A Dtegra210-emc-core.c886 u32 emc_dbg = emc_readl(emc, EMC_DBG); in tegra210_emc_set_shadow_bypass() local
889 emc_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()
891 emc_writel(emc, emc_dbg & ~EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()