| /linux/drivers/gpu/drm/radeon/ |
| H A D | trinity_dpm.c | 947 (old_rps->ecclk != new_rps->ecclk)) { in trinity_set_vce_clock()
949 if (new_rps->evclk || new_rps->ecclk) in trinity_set_vce_clock()
953 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in trinity_set_vce_clock()
1457 u32 evclk, u32 ecclk, u16 *voltage) in trinity_get_vce_clock_voltage() argument
1464 if (((evclk == 0) && (ecclk == 0)) || in trinity_get_vce_clock_voltage()
1472 (ecclk <= table->entries[i].ecclk)) { in trinity_get_vce_clock_voltage()
1508 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in trinity_apply_state_adjust_rules()
1511 new_rps->ecclk = 0; in trinity_apply_state_adjust_rules()
1528 trinity_get_vce_clock_voltage(rdev, new_rps->evclk, new_rps->ecclk, &min_vce_voltage); in trinity_apply_state_adjust_rules()
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| H A D | si_dpm.c | 2871 u32 evclk, u32 ecclk, u16 *voltage) in si_get_vce_clock_voltage() argument
2878 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
2886 (ecclk <= table->entries[i].ecclk)) { in si_get_vce_clock_voltage()
2952 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
2953 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
2957 rps->ecclk = 0; in si_apply_state_adjust_rules()
5879 (old_rps->ecclk != new_rps->ecclk)) { in si_set_vce_clock()
5881 if (new_rps->evclk || new_rps->ecclk) in si_set_vce_clock()
5885 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
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| H A D | kv_dpm.c | 1952 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
1955 new_rps->ecclk = 0; in kv_apply_state_adjust_rules()
2019 new_rps->evclk || new_rps->ecclk; in kv_apply_state_adjust_rules()
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| H A D | r600_dpm.c | 1105 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in r600_parse_extended_power_table()
1120 rdev->pm.dpm.vce_states[i].ecclk = in r600_parse_extended_power_table()
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| H A D | ni.c | 2692 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) in tn_set_vce_clocks() argument
2698 ecclk, false, ÷rs); in tn_set_vce_clocks()
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| H A D | ci_dpm.c | 777 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
780 rps->ecclk = 0; in ci_apply_state_adjust_rules()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu8_hwmgr.c | 79 if (clock <= ptable->entries[i].ecclk) in smu8_get_eclk_level()
87 if (clock >= ptable->entries[i].ecclk) in smu8_get_eclk_level()
537 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0; in smu8_upload_pptable_to_smu()
629 clock = table->entries[level].ecclk; in smu8_init_vce_limit()
631 clock = table->entries[table->count - 1].ecclk; in smu8_init_vce_limit()
1300 ptable->entries[ptable->count - 1].ecclk; in smu8_dpm_update_vce_dpm()
1752 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1810 ecclk = vce_table->entries[vce_index].ecclk; in smu8_read_sensor()
1811 *((uint32_t *)value) = ecclk; in smu8_read_sensor()
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| H A D | smu10_hwmgr.h | 132 uint32_t ecclk; member
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| H A D | smu8_hwmgr.h | 148 uint32_t ecclk; member
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| H A D | smu7_hwmgr.h | 74 uint32_t ecclk; member
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| H A D | vega10_hwmgr.h | 102 uint32_t ecclk; member
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| H A D | vega20_hwmgr.h | 119 uint32_t ecclk; member
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| H A D | processpptables.c | 1251 vce_table->entries[i].ecclk = ((unsigned long)entry->ucECClkHigh << 16) in get_vce_clock_voltage_limit_table()
1684 …vce_state->ecclk = ((uint32_t)vce_clock_info->ucECClkHigh << 16) | le16_to_cpu(vce_clock_info->usE… in get_vce_state_table_entry()
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| H A D | process_pptables_v1_0.c | 1336 vce_state->ecclk = le32_to_cpu(mm_dep_record->ulEClk); in ppt_get_vce_state_table_entry_v1_0()
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| H A D | smu7_hwmgr.c | 4745 … &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk)); in smu7_check_states_equal()
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| H A D | vega10_hwmgr.c | 4928 (vega10_psa->vce_clks.ecclk == vega10_psb->vce_clks.ecclk)); in vega10_check_states_equal()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | power_state.h | 182 unsigned long ecclk; member
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | si_dpm.c | 3041 u32 evclk, u32 ecclk, u16 *voltage) in si_get_vce_clock_voltage() argument
3048 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
3056 (ecclk <= table->entries[i].ecclk)) { in si_get_vce_clock_voltage()
3522 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
3523 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3527 rps->ecclk = 0; in si_apply_state_adjust_rules()
7055 (old_rps->ecclk != new_rps->ecclk)) { in si_set_vce_clock()
7057 dev_dbg(adev->dev, "set VCE clocks: %u, %u\n", new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
7059 if (new_rps->evclk || new_rps->ecclk) { in si_set_vce_clock()
7060 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
[all …]
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| H A D | kv_dpm.c | 2214 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2217 new_rps->ecclk = 0; in kv_apply_state_adjust_rules()
2281 new_rps->evclk || new_rps->ecclk; in kv_apply_state_adjust_rules()
3253 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); in kv_check_state_equal()
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| H A D | legacy_dpm.c | 414 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in amdgpu_parse_extended_power_table()
430 adev->pm.dpm.vce_states[i].ecclk = in amdgpu_parse_extended_power_table()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | soc21.c | 467 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc21_set_vce_clocks() argument
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| H A D | soc15.c | 691 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc15_set_vce_clocks() argument
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| H A D | amdgpu.h | 615 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | kgd_pp_interface.h | 47 u32 ecclk; member
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