| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_rq_dlg_calc_32.c | 45 const display_e2e_pipe_params_st *e2e_pipe_param, in dml32_rq_dlg_get_rq_reg() argument
49 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml32_rq_dlg_get_rq_reg()
76 …pixel_chunk_bytes = get_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // … in dml32_rq_dlg_get_rq_reg()
77 …min_pixel_chunk_bytes = get_min_pixel_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // … in dml32_rq_dlg_get_rq_reg()
82 …meta_chunk_bytes = get_meta_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // Fr… in dml32_rq_dlg_get_rq_reg()
83 …min_meta_chunk_bytes = get_min_meta_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // Fr… in dml32_rq_dlg_get_rq_reg()
85 …dpte_group_bytes = get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); //… in dml32_rq_dlg_get_rq_reg()
86 …mpte_group_bytes = get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // F… in dml32_rq_dlg_get_rq_reg()
96 …p1_pixel_chunk_bytes = get_alpha_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * … in dml32_rq_dlg_get_rq_reg()
129 …detile_buf_size_in_bytes = get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_id… in dml32_rq_dlg_get_rq_reg()
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| H A D | display_rq_dlg_calc_32.h | 46 const display_e2e_pipe_params_st *e2e_pipe_param,
66 display_e2e_pipe_params_st *e2e_pipe_param,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | dml1_display_rq_dlg_calc.c | 1002 const struct _vcs_dpi_display_e2e_pipe_params_st *e2e_pipe_param, in dml1_rq_dlg_get_dlg_params() argument
1009 unsigned int htotal = e2e_pipe_param->pipe.dest.htotal; in dml1_rq_dlg_get_dlg_params()
1010 unsigned int hblank_end = e2e_pipe_param->pipe.dest.hblank_end; in dml1_rq_dlg_get_dlg_params()
1011 unsigned int vblank_start = e2e_pipe_param->pipe.dest.vblank_start; in dml1_rq_dlg_get_dlg_params()
1012 unsigned int vblank_end = e2e_pipe_param->pipe.dest.vblank_end; in dml1_rq_dlg_get_dlg_params()
1013 bool interlaced = e2e_pipe_param->pipe.dest.interlaced; in dml1_rq_dlg_get_dlg_params()
1016 double pclk_freq_in_mhz = e2e_pipe_param->pipe.dest.pixel_rate_mhz; in dml1_rq_dlg_get_dlg_params()
1017 double refclk_freq_in_mhz = e2e_pipe_param->clks_cfg.refclk_mhz; in dml1_rq_dlg_get_dlg_params()
1018 double dppclk_freq_in_mhz = e2e_pipe_param->clks_cfg.dppclk_mhz; in dml1_rq_dlg_get_dlg_params()
1019 double dispclk_freq_in_mhz = e2e_pipe_param->clks_cfg.dispclk_mhz; in dml1_rq_dlg_get_dlg_params()
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| H A D | display_mode_lib.h | 55 const display_e2e_pipe_params_st *e2e_pipe_param,
73 display_e2e_pipe_params_st *e2e_pipe_param,
78 const display_e2e_pipe_params_st *e2e_pipe_param,
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| H A D | dml1_display_rq_dlg_calc.h | 60 const struct _vcs_dpi_display_e2e_pipe_params_st *e2e_pipe_param,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_rq_dlg_calc_21.c | 823 const display_e2e_pipe_params_st *e2e_pipe_param, in dml_rq_dlg_get_dlg_params() argument
833 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
834 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
835 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
836 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
837 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
838 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
976 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml_rq_dlg_get_dlg_params()
977 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1058 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
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| H A D | display_rq_dlg_calc_21.h | 64 const display_e2e_pipe_params_st *e2e_pipe_param,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_rq_dlg_calc_20.c | 47 const display_e2e_pipe_params_st *e2e_pipe_param,
777 const display_e2e_pipe_params_st *e2e_pipe_param, in dml20_rq_dlg_get_dlg_params() argument
787 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20_rq_dlg_get_dlg_params()
788 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20_rq_dlg_get_dlg_params()
789 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20_rq_dlg_get_dlg_params()
790 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
791 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20_rq_dlg_get_dlg_params()
792 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20_rq_dlg_get_dlg_params()
930 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20_rq_dlg_get_dlg_params()
931 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
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| H A D | display_rq_dlg_calc_20v2.c | 47 const display_e2e_pipe_params_st *e2e_pipe_param,
777 const display_e2e_pipe_params_st *e2e_pipe_param, in dml20v2_rq_dlg_get_dlg_params() argument
787 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20v2_rq_dlg_get_dlg_params()
788 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20v2_rq_dlg_get_dlg_params()
789 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20v2_rq_dlg_get_dlg_params()
790 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
791 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20v2_rq_dlg_get_dlg_params()
792 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20v2_rq_dlg_get_dlg_params()
930 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20v2_rq_dlg_get_dlg_params()
931 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
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| H A D | display_rq_dlg_calc_20.h | 64 const display_e2e_pipe_params_st *e2e_pipe_param,
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| H A D | display_rq_dlg_calc_20v2.h | 64 const display_e2e_pipe_params_st *e2e_pipe_param,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_rq_dlg_calc_31.h | 60 const display_e2e_pipe_params_st *e2e_pipe_param,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_rq_dlg_calc_314.h | 61 const display_e2e_pipe_params_st *e2e_pipe_param,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.h | 60 const display_e2e_pipe_params_st *e2e_pipe_param,
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